| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/ |
| H A D | VectorCombine.cpp | 76 ExtractElementInst *getShuffleExtract(ExtractElementInst *Ext0,
79 bool isExtractExtractCheap(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
83 void foldExtExtCmp(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
85 void foldExtExtBinop(ExtractElementInst *Ext0, ExtractElementInst *Ext1,
234 ExtractElementInst *Ext0, ExtractElementInst *Ext1, in getShuffleExtract() argument
236 assert(isa<ConstantInt>(Ext0->getIndexOperand()) && in getShuffleExtract()
240 unsigned Index0 = cast<ConstantInt>(Ext0->getIndexOperand())->getZExtValue(); in getShuffleExtract()
247 Type *VecTy = Ext0->getVectorOperand()->getType(); in getShuffleExtract()
250 TTI.getVectorInstrCost(Ext0->getOpcode(), VecTy, Index0); in getShuffleExtract()
262 return Ext0; in getShuffleExtract()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPULegalizerInfo.cpp | 2567 auto Ext0 = B.buildFPExt(S32, Log, Flags); in legalizeFPow() local
2570 .addUse(Ext0.getReg(0)) in legalizeFPow()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 9687 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
9695 SDValue Res0 = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
9699 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in LowerVecReduce() local
9703 Res = DAG.getNode(BaseOpcode, dl, EltVT, Ext0, Ext1, Op->getFlags()); in LowerVecReduce()
12632 SDValue Ext0 = Mul.getOperand(0); in PerformVQDMULHCombine() local
12634 if (Ext0.getOpcode() != ISD::SIGN_EXTEND || in PerformVQDMULHCombine()
12637 EVT VecVT = Ext0.getOperand(0).getValueType(); in PerformVQDMULHCombine()
12646 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, VecVT, Ext0.getOperand(0), in PerformVQDMULHCombine()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 38810 SDValue Ext0 = in SimplifyDemandedVectorEltsForTargetNode() local
38813 TLO.DAG.getNode(Opc, DL, Ext0.getValueType(), Ext0, Op.getOperand(1)); in SimplifyDemandedVectorEltsForTargetNode()
40765 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpVT, in scalarizeExtEltFP() local
40769 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1, Vec.getOperand(2)); in scalarizeExtEltFP()
40787 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in scalarizeExtEltFP() local
40794 return DAG.getNode(ISD::SELECT, DL, VT, Ext0, Ext1, Ext2); in scalarizeExtEltFP()
50364 SDValue Ext0 = extractSubVector(InVec.getOperand(0), 0, DAG, DL, 128); in combineExtractSubvector() local
50367 return DAG.getNode(InOpcode, DL, VT, Ext0, Ext1, Ext2); in combineExtractSubvector()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 18499 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op0, Index); in scalarizeExtractedBinop() local
18501 return DAG.getNode(Vec.getOpcode(), DL, VT, Ext0, Ext1); in scalarizeExtractedBinop()
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