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Searched refs:DstVT (Results 1 – 25 of 32) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.td1769 ValueType DstVT> {
1788 !if(!eq(DstVT.Size, 1),
1811 class getOutsDPP <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
1813 !if(!eq(DstVT.Size, 1),
1820 class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1822 !if(!eq(DstVT.Size, 1),
1831 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1832 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1845 bit HasOMod, ValueType DstVT = i32> {
1846 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
[all …]
H A DVOP3Instructions.td18 list<dag> ret3 = [(set P.DstVT:$vdst,
23 list<dag> ret2 = [(set P.DstVT:$vdst,
27 list<dag> ret1 = [(set P.DstVT:$vdst,
41 list<dag> ret3 = [(set P.DstVT:$vdst,
46 list<dag> ret2 = [(set P.DstVT:$vdst,
51 list<dag> ret1 = [(set P.DstVT:$vdst,
62 list<dag> ret3 = [(set P.DstVT:$vdst,
67 list<dag> ret2 = [(set P.DstVT:$vdst,
71 list<dag> ret1 = [(set P.DstVT:$vdst,
80 list<dag> ret3 = [(set P.DstVT:$vdst,
[all …]
H A DVOPInstructions.td124 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
506 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
628 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
774 !subst(P.DstRC, P.DstVT, tmp)));
H A DVOP1Instructions.td51 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
98 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
100 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
102 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
H A DVOP2Instructions.td72 let ReadsModeReg = !or(isFloatType<P.DstVT>.ret, isFloatType<P.Src0VT>.ret);
120 [(set P.DstVT:$vdst,
126 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp95 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
707 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend() argument
710 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend()
1245 EVT DstVT = VA.getValVT(); in X86SelectRet() local
1247 if (SrcVT != DstVT) { in X86SelectRet()
1254 assert(DstVT == MVT::i32 && "X86 should always ext to i32"); in X86SelectRet()
1266 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet()
1543 EVT DstVT = TLI.getValueType(DL, I->getType()); in X86SelectZExt() local
1544 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1562 if (DstVT == MVT::i64) { in X86SelectZExt()
[all …]
H A DX86SelectionDAGInfo.cpp279 EVT DstVT = Dst.getValueType(); in emitConstantSizeRepmov() local
283 DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, dl, DstVT)), in emitConstantSizeRepmov()
H A DX86ISelLowering.cpp11539 static bool matchShuffleAsVTRUNC(MVT &SrcVT, MVT &DstVT, MVT VT, in matchShuffleAsVTRUNC() argument
11561 DstVT = MVT::getIntegerVT(EltSizeInBits); in matchShuffleAsVTRUNC()
11564 DstVT = MVT::getVectorVT(DstVT, NumSrcElts); in matchShuffleAsVTRUNC()
11567 DstVT = MVT::getVectorVT(DstVT, 128 / EltSizeInBits); in matchShuffleAsVTRUNC()
11577 static SDValue getAVX512TruncNode(const SDLoc &DL, MVT DstVT, SDValue Src, in getAVX512TruncNode() argument
11581 MVT DstSVT = DstVT.getScalarType(); in getAVX512TruncNode()
11582 unsigned NumDstElts = DstVT.getVectorNumElements(); in getAVX512TruncNode()
11584 unsigned DstEltSizeInBits = DstVT.getScalarSizeInBits(); in getAVX512TruncNode()
11591 return DAG.getNode(ISD::TRUNCATE, DL, DstVT, Src); in getAVX512TruncNode()
11596 return extractSubVector(Trunc, 0, DAG, DL, DstVT.getSizeInBits()); in getAVX512TruncNode()
[all …]
H A DX86ISelDAGToDAG.cpp1211 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1214 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1222 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1238 MVT MemVT = (N->getOpcode() == ISD::FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1249 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, in PreprocessISelDAG()
1267 MVT DstVT = N->getSimpleValueType(0); in PreprocessISelDAG() local
1270 if (SrcVT.isVector() || DstVT.isVector()) in PreprocessISelDAG()
1278 bool DstIsSSE = X86Lowering->isScalarFPTypeInSSEReg(DstVT); in PreprocessISelDAG()
1294 MVT MemVT = (N->getOpcode() == ISD::STRICT_FP_ROUND) ? DstVT : SrcVT; in PreprocessISelDAG()
1323 SDVTList VTs = CurDAG->getVTList(DstVT, MVT::Other); in PreprocessISelDAG()
[all …]
H A DX86InstrAVX512.td7039 RegisterClass SrcRC, X86VectorVTInfo DstVT,
7043 let ExeDomain = DstVT.ExeDomain, Uses = _Uses,
7046 def rr : SI<opc, MRMSrcReg, (outs DstVT.FRC:$dst),
7047 (ins DstVT.FRC:$src1, SrcRC:$src),
7051 def rm : SI<opc, MRMSrcMem, (outs DstVT.FRC:$dst),
7052 (ins DstVT.FRC:$src1, x86memop:$src),
7056 def rr_Int : SI<opc, MRMSrcReg, (outs DstVT.RC:$dst),
7057 (ins DstVT.RC:$src1, SrcRC:$src2),
7059 [(set DstVT.RC:$dst,
7060 (OpNode (DstVT.VT DstVT.RC:$src1), SrcRC:$src2))]>,
[all …]
H A DX86ISelLowering.h1376 std::pair<SDValue, SDValue> BuildFILD(EVT DstVT, EVT SrcVT, const SDLoc &DL,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1062 MVT DstVT; in SelectIToFP() local
1064 if (!isTypeLegal(DstTy, DstVT)) in SelectIToFP()
1067 if (DstVT != MVT::f32 && DstVT != MVT::f64) in SelectIToFP()
1088 if (DstVT == MVT::f32) in SelectIToFP()
1111 if (DstVT == MVT::f32 && !Subtarget->hasFPCVT()) in SelectIToFP()
1133 if (DstVT == MVT::f32) in SelectIToFP()
1187 MVT DstVT, SrcVT; in SelectFPToI() local
1189 if (!isTypeLegal(DstTy, DstVT)) in SelectFPToI()
1192 if (DstVT != MVT::i32 && DstVT != MVT::i64) in SelectFPToI()
1196 if (DstVT == MVT::i64 && !IsSigned && !Subtarget->hasFPCVT() && in SelectFPToI()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp663 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
664 if (SrcVT == DstVT) in SimplifyMultipleUseDemandedBits()
668 unsigned NumDstEltBits = DstVT.getScalarSizeInBits(); in SimplifyMultipleUseDemandedBits()
672 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
694 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
713 return DAG.getBitcast(DstVT, V); in SimplifyMultipleUseDemandedBits()
812 EVT DstVT = Op.getValueType(); in SimplifyMultipleUseDemandedBits() local
813 if (DemandedElts == 1 && DstVT.getSizeInBits() == SrcVT.getSizeInBits() && in SimplifyMultipleUseDemandedBits()
816 return DAG.getBitcast(DstVT, Src); in SimplifyMultipleUseDemandedBits()
6660 EVT DstVT = Node->getValueType(0); in expandFP_TO_SINT() local
[all …]
H A DFastISel.cpp1359 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectCast() local
1361 if (SrcVT == MVT::Other || !SrcVT.isSimple() || DstVT == MVT::Other || in selectCast()
1362 !DstVT.isSimple()) in selectCast()
1367 if (!TLI.isTypeLegal(DstVT)) in selectCast()
1379 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), in selectCast()
1407 MVT DstVT = DstEVT.getSimpleVT(); in selectBitCast() local
1414 if (SrcVT == DstVT) { in selectBitCast()
1416 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1427 ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); in selectBitCast()
1782 EVT DstVT = TLI.getValueType(DL, I->getType()); in selectOperator() local
[all …]
H A DDAGCombiner.cpp551 SDValue foldSubToUSubSat(EVT DstVT, SDNode *N);
3155 static SDValue getTruncatedUSUBSAT(EVT DstVT, EVT SrcVT, SDValue LHS, in getTruncatedUSUBSAT() argument
3158 assert(DstVT.getScalarSizeInBits() <= SrcVT.getScalarSizeInBits() && in getTruncatedUSUBSAT()
3161 if (DstVT == SrcVT) in getTruncatedUSUBSAT()
3162 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
3167 DstVT.getScalarSizeInBits()); in getTruncatedUSUBSAT()
3173 DstVT.getScalarSizeInBits()), in getTruncatedUSUBSAT()
3176 RHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, RHS); in getTruncatedUSUBSAT()
3177 LHS = DAG.getNode(ISD::TRUNCATE, DL, DstVT, LHS); in getTruncatedUSUBSAT()
3178 return DAG.getNode(ISD::USUBSAT, DL, DstVT, LHS, RHS); in getTruncatedUSUBSAT()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DScalarizer.cpp695 VectorType *DstVT = dyn_cast<VectorType>(BCI.getDestTy()); in visitBitCastInst() local
697 if (!DstVT || !SrcVT) in visitBitCastInst()
700 unsigned DstNumElems = cast<FixedVectorType>(DstVT)->getNumElements(); in visitBitCastInst()
709 Res[I] = Builder.CreateBitCast(Op0[I], DstVT->getElementType(), in visitBitCastInst()
715 auto *MidTy = FixedVectorType::get(DstVT->getElementType(), FanOut); in visitBitCastInst()
741 Res[ResI] = Builder.CreateBitCast(V, DstVT->getElementType(), in visitBitCastInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h287 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
289 bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td3608 class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
3610 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3665 class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
3668 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3673 class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
3676 MSAPat<(DstVT (bitconvert SrcVT:$src)),
3681 class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
3683 MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
3685 class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
3687 MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
[all …]
H A DMipsFastISel.cpp1099 MVT DstVT, SrcVT; in selectFPToInt() local
1104 if (!isTypeLegal(DstTy, DstVT)) in selectFPToInt()
1107 if (DstVT != MVT::i32) in selectFPToInt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp876 auto DstVT = TLI->getValueType(DL, Dst); in getExtractWithExtendCost() local
883 if (!VecLT.second.isVector() || !TLI->isTypeLegal(DstVT)) in getExtractWithExtendCost()
889 if (DstVT.getFixedSizeInBits() < SrcVT.getFixedSizeInBits()) in getExtractWithExtendCost()
905 if (DstVT.getSizeInBits() != 64u || SrcVT.getSizeInBits() == 32u) in getExtractWithExtendCost()
H A DAArch64ISelDAGToDAG.cpp1273 EVT DstVT = N->getValueType(0); in tryIndexedLoad() local
1296 DstVT = MVT::i32; in tryIndexedLoad()
1300 if (DstVT == MVT::i64) in tryIndexedLoad()
1306 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1309 DstVT = MVT::i32; in tryIndexedLoad()
1313 if (DstVT == MVT::i64) in tryIndexedLoad()
1319 InsertTo64 = DstVT == MVT::i64; in tryIndexedLoad()
1322 DstVT = MVT::i32; in tryIndexedLoad()
1343 SDNode *Res = CurDAG->getMachineNode(Opcode, dl, MVT::i64, DstVT, in tryIndexedLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMFastISel.cpp1525 MVT DstVT; in SelectIToFP() local
1527 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1559 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
1570 MVT DstVT; in SelectFPToI() local
1572 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1592 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); in SelectFPToI()
H A DARMISelLowering.cpp5894 EVT DstVT = BC->getValueType(0); in CombineVMOVDRRCandidateWithVecOp() local
5902 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in CombineVMOVDRRCandidateWithVecOp()
5912 unsigned DstNumElt = DstVT.getVectorNumElements(); in CombineVMOVDRRCandidateWithVecOp()
5927 *DAG.getContext(), DstVT.getScalarType(), in CombineVMOVDRRCandidateWithVecOp()
5930 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
5948 EVT DstVT = N->getValueType(0); in ExpandBITCAST() local
5951 (DstVT == MVT::f16 || DstVT == MVT::bf16)) in ExpandBITCAST()
5952 return MoveToHPR(SDLoc(N), DAG, MVT::i32, DstVT.getSimpleVT(), in ExpandBITCAST()
5955 if ((DstVT == MVT::i16 || DstVT == MVT::i32) && in ExpandBITCAST()
5958 ISD::TRUNCATE, SDLoc(N), DstVT, in ExpandBITCAST()
[all …]
H A DARMISelLowering.h440 bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp1281 EVT DstVT = TLI.getValueType(DL, CI->getType()); in OptimizeNoopCopyExpression() local
1284 if (SrcVT.isInteger() != DstVT.isInteger()) in OptimizeNoopCopyExpression()
1289 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
1297 if (TLI.getTypeAction(CI->getContext(), DstVT) == in OptimizeNoopCopyExpression()
1299 DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); in OptimizeNoopCopyExpression()
1302 if (SrcVT != DstVT) in OptimizeNoopCopyExpression()

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