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Searched refs:DstReg (Results 1 – 25 of 126) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h57 Register DstReg = MI.getOperand(0).getReg(); in tryCombineAnyExt() local
64 Builder.buildAnyExtOrTrunc(DstReg, TruncSrc); in tryCombineAnyExt()
65 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
77 Builder.buildInstr(ExtMI->getOpcode(), {DstReg}, {ExtSrc}); in tryCombineAnyExt()
78 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
86 const LLT DstTy = MRI.getType(DstReg); in tryCombineAnyExt()
90 DstReg, CstVal.getCImm()->getValue().sext(DstTy.getSizeInBits())); in tryCombineAnyExt()
91 UpdatedDefs.push_back(DstReg); in tryCombineAnyExt()
106 Register DstReg = MI.getOperand(0).getReg(); in tryCombineZExt() local
115 LLT DstTy = MRI.getType(DstReg); in tryCombineZExt()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp69 Register DstReg) { in buildMI() argument
70 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg); in buildMI()
145 Register DstReg = MI.getOperand(0).getReg(); in expandArith() local
152 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandArith()
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic() local
185 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogic()
225 Register DstReg = MI.getOperand(0).getReg(); in expandLogicImm() local
232 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expandLogicImm()
277 Register DstReg = MI.getOperand(0).getReg(); in expand() local
281 TRI->splitReg(DstReg, DstLoReg, DstHiReg); in expand()
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H A DAVRRegisterInfo.cpp102 Register DstReg) { in foldFrameOffset() argument
113 if (DstReg != MI.getOperand(0).getReg()) { in foldFrameOffset()
165 Register DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
166 assert(DstReg != AVR::R29R28 && "Dest reg cannot be the frame pointer"); in eliminateFrameIndex()
179 foldFrameOffset(II, Offset, DstReg); in eliminateFrameIndex()
182 switch (DstReg) { in eliminateFrameIndex()
200 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg) in eliminateFrameIndex()
201 .addReg(DstReg, RegState::Kill) in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp190 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
205 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) { in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
221 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
242 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
252 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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H A DHexagonMCCompound.cpp81 unsigned DstReg, SrcReg, Src1Reg, Src2Reg; in getCompoundCandidateGroup() local
97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
100 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
113 if ((Hexagon::P0 == DstReg || Hexagon::P1 == DstReg) && in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
125 if (HexagonMCInstrInfo::isIntRegForSubInst(DstReg) && in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
136 HexagonMCInstrInfo::isIntRegForSubInst(DstReg)) in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp109 const unsigned DstReg,
122 bool emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
125 bool emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I,
234 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
235 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in selectCopy()
236 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
242 if (DstReg.isPhysical()) { in selectCopy()
250 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy()
279 getRegClass(MRI.getType(DstReg), DstRegBank); in selectCopy()
297 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg); in selectCopy()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSILowerI1Copies.cpp88 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
504 Register DstReg = MI.getOperand(0).getReg(); in lowerCopiesFromI1() local
509 if (isLaneMaskReg(DstReg) || isVreg1(DstReg)) in lowerCopiesFromI1()
516 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); in lowerCopiesFromI1()
520 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) in lowerCopiesFromI1()
564 Register DstReg = MI->getOperand(0).getReg(); in lowerPhis() local
565 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
590 PhiRegisters.insert(DstReg); in lowerPhis()
596 for (MachineInstr &Use : MRI->use_instructions(DstReg)) in lowerPhis()
603 SSAUpdater.Initialize(DstReg); in lowerPhis()
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H A DAMDGPUInstructionSelector.cpp122 Register DstReg = Dst.getReg(); in selectCOPY() local
125 if (isVCC(DstReg, *MRI)) { in selectCOPY()
131 return RBI.constrainGenericRegister(DstReg, *RC, *MRI); in selectCOPY()
136 if (!RBI.constrainGenericRegister(DstReg, *TRI.getBoolRC(), *MRI)) in selectCOPY()
147 BuildMI(*BB, &I, DL, TII.get(MovOpc), DstReg) in selectCOPY()
161 BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_CMP_NE_U32_e64), DstReg) in selectCOPY()
174 if (RC && !RBI.constrainGenericRegister(DstReg, *RC, *MRI)) in selectCOPY()
238 Register DstReg = MRI->createVirtualRegister(&SubRC); in getSubOperand64() local
243 BuildMI(*BB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), DstReg) in getSubOperand64()
246 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(), in getSubOperand64()
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H A DR600ExpandSpecialInstrs.cpp126 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
127 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
130 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
196 Register DstReg = in runOnMachineFunction() local
226 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
230 Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
231 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
232 DstReg = R600::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan); in runOnMachineFunction()
252 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
H A DSIFixSGPRCopies.cpp144 Register DstReg = Copy.getOperand(0).getReg(); in getCopyRegClasses() local
154 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses()
155 ? MRI.getRegClass(DstReg) in getCopyRegClasses()
156 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
180 Register DstReg = MI.getOperand(0).getReg(); in tryChangeVGPRtoSGPRinCopy() local
182 if (!SrcReg.isVirtual() || !DstReg.isVirtual()) in tryChangeVGPRtoSGPRinCopy()
185 for (const auto &MO : MRI.reg_nodbg_operands(DstReg)) { in tryChangeVGPRtoSGPRinCopy()
199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
222 Register DstReg = MI.getOperand(0).getReg(); in foldVGPRCopyIntoRegSequence() local
223 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) in foldVGPRCopyIntoRegSequence()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp139 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
142 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
146 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
159 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
161 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
176 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
178 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
187 Register DstReg = Dst.getReg(); in runOnMachineFunction() local
190 if (DstReg.isVirtual() && SrcReg.isVirtual()) { in runOnMachineFunction()
194 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
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H A DHexagonInstrInfo.cpp1053 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1060 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg) in expandPostRAPseudo()
1068 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1070 copyPhysReg(MBB, MI, DL, DstReg, SrcSubLo, MI.getOperand(1).isKill()); in expandPostRAPseudo()
1077 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1079 copyPhysReg(MBB, MI, DL, DstReg, SrcSubHi, MI.getOperand(1).isKill()); in expandPostRAPseudo()
1085 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1092 BuildMI(MBB, MI, DL, get(NewOpc), DstReg) in expandPostRAPseudo()
1100 Register DstReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1109 HRI.getSubReg(DstReg, Hexagon::vsub_lo)) in expandPostRAPseudo()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp122 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
127 if (DstReg == AArch64::XZR || DstReg == AArch64::WZR) { in expandMOVImm()
158 .addReg(DstReg, RegState::Define | in expandMOVImm()
166 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm() local
169 .addReg(DstReg, in expandMOVImm()
173 .addReg(DstReg) in expandMOVImm()
404 unsigned DstReg = MI.getOperand(0).getReg(); in expand_DestructiveOp() local
408 assert(DstReg != MI.getOperand(3).getReg()); in expand_DestructiveOp()
415 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
428 if (DstReg == MI.getOperand(3).getReg()) { in expand_DestructiveOp()
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H A DAArch64RedundantCopyElimination.cpp186 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
195 SrcReg != DstReg) { in knownRegValInBlock()
209 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
214 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
218 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
252 MCPhysReg DstReg = PredI.getOperand(0).getReg(); in knownRegValInBlock() local
253 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR) in knownRegValInBlock()
258 if (!DomBBClobberedRegs.available(DstReg)) in knownRegValInBlock()
263 KnownRegs.push_back(RegImm(DstReg, 0)); in knownRegValInBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp60 MachineInstr &MI, Register &SrcReg, Register &DstReg,
62 void processDstReg(MachineRegisterInfo *MRI, Register &DstReg,
161 Register &DstReg, const GlobalValue *GVal, bool IsAma) { in processCandidate() argument
162 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) { in processCandidate()
170 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processCandidate()
180 processDstReg(MRI, TmpReg, DstReg, GVal, false, IsAma); in processCandidate()
185 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg) in processCandidate()
191 processDstReg(MRI, DstReg, SrcReg, GVal, true, IsAma); in processCandidate()
195 Register &DstReg, Register &SrcReg, const GlobalValue *GVal, in processDstReg() argument
197 auto Begin = MRI->use_begin(DstReg), End = MRI->use_end(); in processDstReg()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp154 void scanUses(Register DstReg);
268 Register &SrcReg, Register &DstReg, bool &IsSrcPhys, in isCopyToReg() argument
271 DstReg = 0; in isCopyToReg()
273 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
276 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
283 IsDstPhys = DstReg.isPhysical(); in isCopyToReg()
349 Register SrcReg, DstReg; in isKilled() local
352 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
360 static bool isTwoAddrUse(MachineInstr &MI, Register Reg, Register &DstReg) { in isTwoAddrUse() argument
367 DstReg = MI.getOperand(ti).getReg(); in isTwoAddrUse()
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H A DRegisterCoalescer.cpp300 void updateRegDefsUses(Register SrcReg, Register DstReg, unsigned SubIdx);
439 SrcReg = DstReg = Register(); in setRegisters()
523 DstReg = Dst; in setRegisters()
528 if (Register::isPhysicalRegister(DstReg)) in flip()
530 std::swap(SrcReg, DstReg); in flip()
553 if (DstReg.isPhysical()) { in isCoalescable()
562 return DstReg == Dst; in isCoalescable()
564 return Register(TRI.getSubReg(DstReg, SrcSub)) == Dst; in isCoalescable()
567 if (DstReg != Dst) in isCoalescable()
1265 Register DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); in reMaterializeTrivialDef() local
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H A DOptimizePHIs.cpp101 Register DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local
114 if (SrcReg == DstReg) in IsSingleValuePHICycle()
145 Register DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local
146 assert(Register::isVirtualRegister(DstReg) && in IsDeadPHICycle()
157 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) { in IsDeadPHICycle()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp113 static bool forwardCopyWillClobberTuple(unsigned DstReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
117 return ((DstReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
122 const DebugLoc &DL, MCRegister DstReg, in copyPhysReg() argument
124 if (RISCV::GPRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
125 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
137 if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
140 } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
143 } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
146 } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
148 } else if (RISCV::VRM2RegClass.contains(DstReg, SrcReg)) { in copyPhysReg()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp642 const DebugLoc &DL, MCRegister DstReg, in copyPhysReg() argument
647 if (M68k::XR32RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
649 else if (M68k::XR16RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
651 else if (M68k::DR8RegClass.contains(DstReg, SrcReg)) in copyPhysReg()
655 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
668 if (M68k::XR16RegClass.contains(DstReg)) in copyPhysReg()
670 else if (M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
673 M68k::XR32RegClass.contains(DstReg)) in copyPhysReg()
677 BuildMI(MBB, MI, DL, get(Opc), DstReg) in copyPhysReg()
684 bool ToCCR = DstReg == M68k::CCR; in copyPhysReg()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp199 void LegalizerHelper::insertParts(Register DstReg, in insertParts() argument
208 MIRBuilder.buildMerge(DstReg, PartRegs); in insertParts()
213 MIRBuilder.buildConcatVectors(DstReg, PartRegs); in insertParts()
215 MIRBuilder.buildBuildVector(DstReg, PartRegs); in insertParts()
236 DstReg : MRI.createGenericVirtualRegister(ResultTy); in insertParts()
369 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, in buildWidenedRemergeToDst() argument
371 LLT DstTy = MRI.getType(DstReg); in buildWidenedRemergeToDst()
377 MIRBuilder.buildMerge(DstReg, RemergeRegs); in buildWidenedRemergeToDst()
383 MIRBuilder.buildTrunc(DstReg, Remerge); in buildWidenedRemergeToDst()
390 UnmergeDefs[0] = DstReg; in buildWidenedRemergeToDst()
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H A DInstructionSelect.cpp169 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction()
179 assert(canReplaceReg(DstReg, SrcReg, MRI) && in runOnMachineFunction()
182 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
222 Register DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
224 Register::isVirtualRegister(DstReg)) { in runOnMachineFunction()
226 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction()
228 MRI.replaceRegWith(DstReg, SrcReg); in runOnMachineFunction()
H A DCombinerHelper.cpp154 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy() local
156 return canReplaceReg(DstReg, SrcReg, MRI); in matchCombineCopy()
159 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy() local
162 replaceRegWith(MRI, DstReg, SrcReg); in applyCombineCopy()
224 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors() local
226 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineConcatVectors()
239 replaceRegWith(MRI, DstReg, NewDstReg); in applyCombineConcatVectors()
329 Register DstReg = MI.getOperand(0).getReg(); in applyCombineShuffleVector() local
331 Register NewDstReg = MRI.cloneVirtualRegister(DstReg); in applyCombineShuffleVector()
339 replaceRegWith(MRI, DstReg, NewDstReg); in applyCombineShuffleVector()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp229 bool loadImmediate(int64_t ImmValue, unsigned DstReg, unsigned SrcReg,
233 bool loadAndAddSymbolAddress(const MCExpr *SymExpr, unsigned DstReg,
251 bool expandLoadAddress(unsigned DstReg, unsigned BaseReg,
2182 MCOperand &DstReg = Inst.getOperand(0); in processInstruction() local
2186 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) && in processInstruction()
2190 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset, in processInstruction()
2698 bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, in loadImmediate() argument
2728 unsigned TmpReg = DstReg; in loadImmediate()
2730 getContext().getRegisterInfo()->isSuperOrSubRegisterEq(DstReg, SrcReg)) { in loadImmediate()
2747 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp149 MachineInstr *emitLaneInsert(Optional<Register> DstReg, Register SrcReg,
262 MachineInstr *emitExtractVectorElt(Optional<Register> DstReg,
775 const Register DstReg = I.getOperand(0).getReg(); in isValidCopy() local
777 const unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in isValidCopy()
833 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy() local
835 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in getRegClassesForCopy()
837 unsigned DstSize = RBI.getSizeInBits(DstReg, MRI, TRI); in getRegClassesForCopy()
858 Register DstReg = I.getOperand(0).getReg(); in selectCopy() local
860 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
870 << RBI.getSizeInBits(DstReg, MRI, TRI) << '\n'); in selectCopy()
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