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Searched refs:DstRC (Results 1 – 25 of 49) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp154 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses() local
158 return std::make_pair(SrcRC, DstRC); in getCopyRegClasses()
162 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy() argument
164 return SrcRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(DstRC) && in isVGPRToSGPRCopy()
169 const TargetRegisterClass *DstRC, in isSGPRToVGPRCopy() argument
171 return DstRC != &AMDGPU::VReg_1RegClass && TRI.isSGPRClass(SrcRC) && in isSGPRToVGPRCopy()
172 TRI.hasVectorRegisters(DstRC); in isSGPRToVGPRCopy()
237 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence() local
238 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); in foldVGPRCopyIntoRegSequence()
240 if (!isSGPRToVGPRCopy(SrcRC, DstRC, *TRI)) in foldVGPRCopyIntoRegSequence()
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H A DAMDGPUInstructionSelector.cpp104 const TargetRegisterClass *DstRC in constrainCopyLikeIntrin() local
108 if (!DstRC || DstRC != SrcRC) in constrainCopyLikeIntrin()
111 return RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI) && in constrainCopyLikeIntrin()
477 const TargetRegisterClass *DstRC = in selectG_EXTRACT() local
479 if (!DstRC || !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_EXTRACT()
516 const TargetRegisterClass *DstRC = in selectG_MERGE_VALUES() local
518 if (!DstRC) in selectG_MERGE_VALUES()
521 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES()
535 if (!RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) in selectG_MERGE_VALUES()
577 const TargetRegisterClass *DstRC = in selectG_UNMERGE_VALUES() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp110 const TargetRegisterClass *DstRC,
250 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg); in selectCopy() local
252 if (SrcRC != DstRC) { in selectCopy()
254 Register ExtSrc = MRI.createVirtualRegister(DstRC); in selectCopy()
278 const TargetRegisterClass *DstRC = in selectCopy() local
288 if (DstRC != SrcRC) { in selectCopy()
289 I.getOperand(1).setSubReg(getSubRegIndex(DstRC)); in selectCopy()
298 if (!OldRC || !DstRC->hasSubClassEq(OldRC)) { in selectCopy()
299 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
684 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC, in canTurnIntoCOPY() argument
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H A DX86InstrMMX.td123 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
126 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
127 [(set DstRC:$dst, (Int SrcRC:$src))], d>,
129 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
130 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>,
135 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
137 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst),
138 (ins DstRC:$src1, SrcRC:$src2), asm,
139 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>,
141 def irm : MMXPI<opc, MRMSrcMem, (outs DstRC:$dst),
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp151 const TargetRegisterClass *DstRC, in isCrossCopy() argument
156 if (DstRC == SrcRC) in isCrossCopy()
181 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, in isCrossCopy()
184 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); in isCrossCopy()
186 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); in isCrossCopy()
187 return !TRI.getCommonSubClass(SrcRC, DstRC); in isCrossCopy()
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes() local
436 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO); in determineInitialUsedLanes()
484 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in isUndefInput() local
485 *CrossCopy = isCrossCopy(*MRI, MI, DstRC, MO); in isUndefInput()
H A DPeepholeOptimizer.cpp477 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
479 if (!DstRC) in INITIALIZE_PASS_DEPENDENCY()
585 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
H A DRegisterCoalescer.cpp479 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); in setRegisters() local
487 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
494 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
498 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
501 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
516 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1351 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in reMaterializeTrivialDef() local
1353 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1882 auto DstRC = MRI->getRegClass(CP.getDstReg()); in joinCopy() local
1887 std::swap(SrcRC, DstRC); in joinCopy()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp176 const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg); in runOnMachineFunction() local
177 if (DstRC) in runOnMachineFunction()
178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
226 auto DstRC = MRI.getRegClass(DstReg); in runOnMachineFunction() local
227 if (SrcRC == DstRC) { in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DFastISelEmitter.cpp204 const CodeGenRegisterClass *DstRC = nullptr; in initialize() local
282 if (DstRC) { in initialize()
283 if (DstRC != RC && !DstRC->hasSubClass(RC)) in initialize()
286 DstRC = RC; in initialize()
485 const CodeGenRegisterClass *DstRC = nullptr; in collectPatterns() local
493 DstRC = &Target.getRegisterClass(Op0Rec); in collectPatterns()
494 if (!DstRC) in collectPatterns()
533 DstRC)) in collectPatterns()
583 DstRC, in collectPatterns()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMicroMips32r6InstrInfo.td657 class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
660 dag OutOperandList = (outs DstRC:$rs);
668 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
672 dag OutOperandList = (outs DstRC:$fs);
674 list<dag> Pattern = [(set DstRC:$fs, (OpNode SrcRC:$rt))];
680 string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
682 dag InOperandList = (ins DstRC:$fs_in, SrcRC:$rt);
683 dag OutOperandList = (outs DstRC:$fs);
693 class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC,
696 dag OutOperandList = (outs DstRC:$impl);
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H A DMipsInstrFPU.td128 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
130 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
131 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
135 class CVT_PS_S_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
138 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs, SrcRC:$ft),
140 [(set DstRC:$fd, (OpNode SrcRC:$fs, SrcRC:$ft))], Itin, FrmFR, opstr>,
162 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
164 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
165 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT {
169 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXCopy.cpp120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass; in processBlock() local
127 Register NewVReg = MRI.createVirtualRegister(DstRC); in processBlock()
H A DPPCVSXSwapRemoval.cpp922 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in handleSpecialSwappables() local
923 Register NewVReg = MRI->createVirtualRegister(DstRC); in handleSpecialSwappables()
936 if (DstRC == &PPC::VRRCRegClass) { in handleSpecialSwappables()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp139 const TargetRegisterClass *DstRC,
865 const TargetRegisterClass *DstRC; in selectCopy() local
866 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); in selectCopy()
868 if (!DstRC) { in selectCopy()
908 unsigned DstSize = TRI.getRegSizeInBits(*DstRC); in selectCopy()
916 getSubRegForClass(DstRC, TRI, SubReg); in selectCopy()
920 copySubReg(I, MRI, RBI, Copy.getReg(0), DstRC, SubReg); in selectCopy()
927 copySubReg(I, MRI, RBI, SrcReg, DstRC, SubReg); in selectCopy()
956 if (!RBI.constrainGenericRegister(DstReg, *DstRC, MRI)) { in selectCopy()
2829 const TargetRegisterClass *DstRC = in select() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp282 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
290 return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); in shouldCoalesce()
H A DAVRRegisterInfo.h57 const TargetRegisterClass *DstRC,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
H A DHexagonRegisterInfo.cpp349 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp159 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
164 DstRC = MRI->getRegClass(VRBase); in EmitCopyFromReg()
168 DstRC = UseRC; in EmitCopyFromReg()
170 DstRC = TLI->getRegClassFor(VT, Node->isDivergent()); in EmitCopyFromReg()
179 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
614 const TargetRegisterClass *DstRC = in EmitCopyToRegClassNode() local
616 Register NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.h160 const TargetRegisterClass *DstRC,
H A DSystemZRegisterInfo.cpp379 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
387 (getRegSizeInBits(*SrcRC) <= 64 || getRegSizeInBits(*DstRC) <= 64))) in shouldCoalesce()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.h134 unsigned SubReg, const TargetRegisterClass *DstRC,
H A DAArch64RegisterInfo.cpp783 const TargetRegisterClass *DstRC, unsigned DstSubReg, in shouldCoalesce() argument
786 ((DstRC->getID() == AArch64::GPR64RegClassID) || in shouldCoalesce()
787 (DstRC->getID() == AArch64::GPR64commonRegClassID)) && in shouldCoalesce()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp857 const TargetRegisterClass *DstRC, in shouldCoalesce() argument
869 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 && in shouldCoalesce()
878 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC); in shouldCoalesce()
H A DARMBaseRegisterInfo.h208 const TargetRegisterClass *DstRC,

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