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Searched refs:DstRB (Results 1 – 4 of 4) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp622 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping() local
624 if (!DstRB) in getInstrMapping()
625 DstRB = SrcRB; in getInstrMapping()
627 SrcRB = DstRB; in getInstrMapping()
630 assert(DstRB && SrcRB && "Both RegBank were nullptr"); in getInstrMapping()
633 DefaultMappingID, copyCost(*DstRB, *SrcRB, Size), in getInstrMapping()
634 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
647 const RegisterBank &DstRB = in getInstrMapping() local
652 DefaultMappingID, copyCost(DstRB, SrcRB, Size), in getInstrMapping()
653 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
H A DAArch64InstructionSelector.cpp263 const RegisterBank &DstRB, LLT ScalarTy,
2478 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
2479 assert(SrcRB.getID() == DstRB.getID() && "Wrong extract regbank!"); in select()
2492 DstReg, DstRB, LLT::scalar(64), SrcReg, LaneIdx, MIB); in select()
2819 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select() local
2822 if (DstRB.getID() != SrcRB.getID()) { in select()
2828 if (DstRB.getID() == AArch64::GPRRegBankID) { in select()
2830 getRegClassForTypeOnBank(DstTy, DstRB, RBI); in select()
2862 } else if (DstRB.getID() == AArch64::FPRRegBankID) { in select()
2871 DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB); in select()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp283 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_AND_OR_XOR() local
284 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
285 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
288 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR()
310 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectG_ADD_SUB() local
311 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; in selectG_ADD_SUB()
1159 const RegisterBank *DstRB = RBI.getRegBank(DstReg, *MRI, TRI); in selectGroupStaticSize() local
1160 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize()
1840 const RegisterBank *DstRB; in selectG_TRUNC() local
1844 DstRB = SrcRB; in selectG_TRUNC()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp719 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt() local
722 if (DstRB.getID() != SrcRB.getID()) { in selectTruncOrPtrToInt()
728 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectTruncOrPtrToInt()
740 if (DstRB.getID() != X86::GPRRegBankID) in selectTruncOrPtrToInt()
848 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext() local
851 assert(DstRB.getID() == SrcRB.getID() && in selectAnyext()
857 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB); in selectAnyext()
866 if (DstRB.getID() != X86::GPRRegBankID) in selectAnyext()