Searched refs:DstHi (Results 1 – 7 of 7) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 1076 auto DstHi = MRI.createGenericVirtualRegister(s64); in legalizeAtomicCmpxchg128() local
1125 MIRBuilder.buildExtract({DstHi}, {CASDst}, 64); in legalizeAtomicCmpxchg128()
1131 CAS = MIRBuilder.buildInstr(AArch64::CMP_SWAP_128, {DstLo, DstHi, Scratch}, in legalizeAtomicCmpxchg128()
1142 MIRBuilder.buildMerge(MI.getOperand(0), {DstLo, DstHi}); in legalizeAtomicCmpxchg128()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC() local
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
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| H A D | MipsSEInstrInfo.cpp | 748 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() local
750 HiInst.addReg(DstHi, RegState::Define); in expandPseudoMTLoHi()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 359 Register DstHi = MRI->createVirtualRegister(&HalfRC); in selectG_ADD_SUB() local
365 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi) in selectG_ADD_SUB()
376 MachineInstr *Addc = BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_ADDC_U32_e64), DstHi) in selectG_ADD_SUB()
390 .addReg(DstHi) in selectG_ADD_SUB()
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| H A D | SIInstrInfo.cpp | 1698 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() local
1722 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
1744 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi) in expandPostRAPseudo()
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| H A D | SIISelLowering.cpp | 4132 Register DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
4144 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi) in EmitInstrWithCustomInserter()
4154 .addReg(DstHi) in EmitInstrWithCustomInserter()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonFrameLowering.cpp | 1985 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi); in expandLoadVec2() local
2010 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
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