Searched refs:DppCtrl (Results 1 – 5 of 5) sorted by relevance
819 } else if (Imm <= DppCtrl::QUAD_PERM_LAST) { in printDPPCtrl()825 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) && in printDPPCtrl()826 (Imm <= DppCtrl::ROW_SHL_LAST)) { in printDPPCtrl()829 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) && in printDPPCtrl()830 (Imm <= DppCtrl::ROW_SHR_LAST)) { in printDPPCtrl()833 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) && in printDPPCtrl()834 (Imm <= DppCtrl::ROW_ROR_LAST)) { in printDPPCtrl()837 } else if (Imm == DppCtrl::WAVE_SHL1) { in printDPPCtrl()843 } else if (Imm == DppCtrl::WAVE_ROL1) { in printDPPCtrl()849 } else if (Imm == DppCtrl::WAVE_SHR1) { in printDPPCtrl()[all …]
403 auto *DppCtrl = TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl); in combineDPPMov() local404 assert(DppCtrl && DppCtrl->isImm()); in combineDPPMov()405 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl->getImm())) { in combineDPPMov()
4258 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 || in verifyInstruction()4259 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST || in verifyInstruction()4260 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) || in verifyInstruction()4261 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) || in verifyInstruction()4262 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) || in verifyInstruction()4263 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST) || in verifyInstruction()4264 (DC >= DppCtrl::DPP_UNUSED8_FIRST && DC <= DppCtrl::DPP_UNUSED8_LAST)) { in verifyInstruction()4268 if (DC >= DppCtrl::WAVE_SHL1 && DC <= DppCtrl::WAVE_ROR1 && in verifyInstruction()4274 if (DC >= DppCtrl::BCAST15 && DC <= DppCtrl::BCAST31 && in verifyInstruction()4280 if (DC >= DppCtrl::ROW_SHARE_FIRST && DC <= DppCtrl::ROW_XMASK_LAST && in verifyInstruction()[all …]
675 enum DppCtrl : unsigned { enum
3953 unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm(); in validateDPP() local3955 if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) { in validateDPP()7654 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) || in isDPPCtrl()7655 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) || in isDPPCtrl()7656 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) || in isDPPCtrl()7657 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) || in isDPPCtrl()7658 (Imm == DppCtrl::WAVE_SHL1) || in isDPPCtrl()7659 (Imm == DppCtrl::WAVE_ROL1) || in isDPPCtrl()7660 (Imm == DppCtrl::WAVE_SHR1) || in isDPPCtrl()7661 (Imm == DppCtrl::WAVE_ROR1) || in isDPPCtrl()[all …]