Searched refs:DestSub1 (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1699 Register DestSub1 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local
1710 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1) in computeBase()
1724 .addReg(DestSub1) in computeBase()
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| H A D | SIInstrInfo.cpp | 6355 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
6356 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
6359 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
6365 .addReg(DestSub1) in splitScalar64BitUnaryOp()
6391 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitAddSub() local
6428 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1) in splitScalar64BitAddSub()
6438 .addReg(DestSub1) in splitScalar64BitAddSub()
6495 Register DestSub1 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitBinaryOp() local
6496 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
6504 .addReg(DestSub1) in splitScalar64BitBinaryOp()
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| H A D | SIISelLowering.cpp | 3918 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
3935 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1).add(Src0Sub1).add(Src1Sub1); in EmitInstrWithCustomInserter()
3939 .addReg(DestSub1) in EmitInstrWithCustomInserter()
3956 Register DestSub1 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
3996 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1) in EmitInstrWithCustomInserter()
4006 .addReg(DestSub1) in EmitInstrWithCustomInserter()
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