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Searched refs:DestReg (Results 1 – 25 of 112) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
130 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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H A DThumb1InstrInfo.cpp41 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
51 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
52 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
62 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
108 Register DestReg, int FI, in loadRegFromStackSlot() argument
113 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
117 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
126 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
H A DThumb2InstrInfo.cpp134 Register DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
136 if (!DestReg.isVirtual()) in optimizeSelect()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
152 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
155 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
156 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
158 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
208 Register DestReg, int FI, in loadRegFromStackSlot() argument
220 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
232 if (Register::isVirtualRegister(DestReg)) { in loadRegFromStackSlot()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp89 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
91 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
110 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
113 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
130 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
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H A DSystemZInstrInfo.cpp154 Register DestReg = MI.getOperand(0).getReg(); in expandRIEPseudo() local
156 bool DestIsHigh = SystemZ::isHighReg(DestReg); in expandRIEPseudo()
161 if (DestReg != SrcReg) { in expandRIEPseudo()
162 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg, in expandRIEPseudo()
165 MI.getOperand(1).setReg(DestReg); in expandRIEPseudo()
248 const DebugLoc &DL, unsigned DestReg, in emitGRX32Move() argument
253 bool DestIsHigh = SystemZ::isHighReg(DestReg); in emitGRX32Move()
262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg) in emitGRX32Move()
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg) in emitGRX32Move()
267 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp383 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
388 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
406 if (DestReg != BaseReg) in optTwoAddrLEA()
411 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
432 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
435 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
442 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp307 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195 unsigned DestReg);
197 unsigned DestReg);
394 unsigned DestReg = createResultReg(RC); in materializeFP() local
396 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
397 return DestReg; in materializeFP()
400 unsigned DestReg = createResultReg(RC); in materializeFP() local
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H A DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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H A DMips16InstrInfo.cpp71 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
85 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
92 if (DestReg) in copyPhysReg()
93 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
126 Register DestReg, int FI, in loadRegFromStack() argument
138 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) in loadRegFromStack()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp221 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
240 .addReg(DestReg) in doAtomicBinOpExpansion()
257 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
283 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
311 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
316 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
321 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp268 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
269 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
270 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
276 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
278 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
355 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
362 MO.getReg() == DestReg) in AssignSlot()
368 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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H A DAMDGPUMachineCFGStructurizer.cpp43 unsigned DestReg;
58 PHIInfoElementT *findPHIInfoElement(unsigned DestReg);
65 void addDest(unsigned DestReg, const DebugLoc &DL);
67 void deleteDef(unsigned DestReg);
68 void addSource(unsigned DestReg, unsigned SourceReg,
70 void removeSource(unsigned DestReg, unsigned SourceReg,
73 unsigned &DestReg);
75 unsigned getNumSources(unsigned DestReg);
112 return Info->DestReg; in phiInfoElementGetDest()
117 Info->DestReg = NewDef; in phiInfoElementSetDef()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp79 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
86 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
35 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
38 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
149 Register DestReg, int FI, in loadRegFromStackSlot() argument
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h336 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
338 .addReg(DestReg, RegState::Define); in BuildMI()
347 Register DestReg) { in BuildMI() argument
351 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
363 Register DestReg) { in BuildMI() argument
367 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
372 Register DestReg) { in BuildMI() argument
376 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), DL, MCID, DestReg); in BuildMI()
377 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg); in BuildMI()
382 Register DestReg) { in BuildMI() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp43 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
51 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
57 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
67 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
69 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
71 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
77 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
161 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp614 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
617 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
619 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
620 ActiveChains[DestReg] = G.get(); in scanInstruction()
627 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
632 if (DestReg != AccumReg) in scanInstruction()
647 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
649 if (DestReg != AccumReg) { in scanInstruction()
650 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
663 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
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H A DAArch64InstrInfo.cpp3167 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg, in forwardCopyWillClobberTuple() argument
3171 return ((DestReg - SrcReg) & 0x1f) < NumRegs; in forwardCopyWillClobberTuple()
3176 const DebugLoc &DL, MCRegister DestReg, in copyPhysRegTuple() argument
3182 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyPhysRegTuple()
3195 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
3203 DebugLoc DL, unsigned DestReg, in copyGPRRegTuple() argument
3211 uint16_t DestEncoding = TRI->getEncodingValue(DestReg); in copyGPRRegTuple()
3219 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyGPRRegTuple()
3228 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
3230 if (AArch64::GPR32spRegClass.contains(DestReg) && in copyPhysReg()
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H A DAArch64AsmPrinter.cpp886 Register DestReg = MI.getOperand(0).getReg(); in LowerJumpTableDest() local
910 .addReg(DestReg) in LowerJumpTableDest()
933 .addReg(DestReg) in LowerJumpTableDest()
934 .addReg(DestReg) in LowerJumpTableDest()
1092 Register DestReg = MI.getOperand(0).getReg(); in EmitFMov0() local
1095 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31) in EmitFMov0()
1096 DestReg = AArch64::D0 + (DestReg - AArch64::H0); in EmitFMov0()
1097 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31) in EmitFMov0()
1098 DestReg = AArch64::D0 + (DestReg - AArch64::S0); in EmitFMov0()
1100 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31); in EmitFMov0()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp328 MCRegister DestReg, MCRegister SrcReg, bool KillSrc, in copyPhysSubRegs() argument
335 Register SubDest = TRI->getSubReg(DestReg, SubRegIdx[Idx]); in copyPhysSubRegs()
354 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysSubRegs()
361 MCRegister DestReg, MCRegister SrcReg, in copyPhysReg() argument
364 if (IsAliasOfSX(SrcReg) && IsAliasOfSX(DestReg)) { in copyPhysReg()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
368 } else if (VE::V64RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
387 } else if (VE::VMRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp65 Register DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
92 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
95 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
102 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp159 bool isZExt, unsigned DestReg,
169 unsigned DestReg, bool IsZExt);
819 bool IsZExt, unsigned DestReg, in PPCEmitCmp() argument
945 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg) in PPCEmitCmp()
986 unsigned DestReg; in SelectFPTrunc() local
989 DestReg = createResultReg(&PPC::GPRCRegClass); in SelectFPTrunc()
991 TII.get(PPC::EFSCFD), DestReg) in SelectFPTrunc()
994 DestReg = createResultReg(&PPC::VSSRCRegClass); in SelectFPTrunc()
996 TII.get(PPC::XSRSP), DestReg) in SelectFPTrunc()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp58 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
64 Register::isVirtualRegister(DestReg) in copyPhysReg()
65 ? MRI.getRegClass(DestReg) in copyPhysReg()
66 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
86 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp333 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
335 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
339 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
346 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
350 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
383 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
396 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()

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