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Searched refs:Defs (Results 1 – 25 of 191) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrSystem.td25 let hasSideEffects = 1, Defs = [CC] in {
31 let Uses = [R2L], Defs = [R2L] in
119 let hasSideEffects = 1, Defs = [CC] in
123 let hasSideEffects = 1, Defs = [CC] in
139 let hasSideEffects = 1, mayStore = 1, Uses = [R0D], Defs = [R0D, CC] in
143 let mayLoad = 1, mayStore = 1, Defs = [CC] in {
161 let Predicates = [FeatureEnhancedDAT2], hasSideEffects = 1, Defs = [CC] in
169 let hasSideEffects = 1, Defs = [CC] in {
175 let hasSideEffects = 1, Defs = [CC] in
179 let hasSideEffects = 1, Defs = [CC] in {
[all …]
H A DSystemZInstrHFP.td21 let Defs = [CC] in {
60 let Defs = [CC] in {
71 let Defs = [CC] in {
77 let Defs = [CC] in {
88 let Defs = [CC] in {
95 let Defs = [CC] in {
102 let Defs = [CC] in {
131 let Defs = [CC] in {
142 let Defs = [CC] in {
152 let Defs = [CC] in {
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H A DSystemZInstrDFP.td22 let Uses = [FPC], Defs = [CC] in {
66 let Uses = [FPC], Defs = [CC] in {
78 let Uses = [FPC], Defs = [CC] in {
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
145 let Uses = [FPC], Defs = [CC] in {
157 let Uses = [FPC], Defs = [CC] in {
216 let Uses = [FPC], Defs = [CC] in {
222 let Uses = [FPC], Defs = [CC] in {
228 let Defs = [CC] in {
234 let Defs = [CC] in {
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H A DSystemZInstrInfo.td35 let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
41 let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1,
133 let Defs = [CC] in {
157 let Defs = [CC] in {
191 let Defs = [CC] in {
206 let Defs = [CC] in {
273 let isCall = 1, Defs = [CC] in {
282 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in {
293 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in {
302 let isCall = 1, Defs = [R14D, CC] in {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {} in DefUseInfo()
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
158 void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, in getDefsUses() argument
165 expandReg(*R++, Defs); in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps() local
189 Defs.reset(); in buildMaps()
191 getDefsUses(MI, Defs, Uses); in buildMaps()
192 DUM.insert(std::make_pair(Index, DefUseInfo(Defs, Uses))); in buildMaps()
[all …]
H A DHexagonPseudo.td81 let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
177 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = [R16],
182 Defs = [PC, R31, R6, R7, P0] in
219 let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
66 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
152 bool SIFormMemoryClauses::canBundle(const MachineInstr &MI, const RegUse &Defs, in canBundle() argument
170 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
219 RegUse &Defs, RegUse &Uses) const { in collectRegUses() argument
230 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
247 RegUse &Defs, RegUse &Uses, in processRegUses() argument
249 if (!canBundle(MI, Defs, Uses)) in processRegUses()
255 collectRegUses(MI, Defs, Uses); in processRegUses()
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H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anon9dbd22ff0111::SIPostRABundler
83 for (Register Def : Defs) in isDependentLoad()
140 assert(Defs.empty()); in runOnMachineFunction()
143 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
155 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
208 Defs.clear(); in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td98 class Defs<list<Register> Regs> {
99 list<Register> Defs = Regs;
561 Defs<[DSPOutFlag20]>;
565 IsCommutable, Defs<[DSPOutFlag20]>;
569 Defs<[DSPOutFlag20]>;
573 Defs<[DSPOutFlag20]>;
577 Defs<[DSPOutFlag20]>;
581 IsCommutable, Defs<[DSPOutFlag20]>;
585 Defs<[DSPOutFlag20]>;
589 Defs<[DSPOutFlag20]>;
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H A DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon845733c10111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon845733c10111::MemDefsUses
345 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
354 Defs.set(Mips::RA); in init()
360 Defs.reset(Mips::AT); in init()
371 Defs.set(Mips::RA); in setCallerSaved()
372 Defs.set(Mips::RA_64); in setCallerSaved()
386 Defs |= CallerSavedRegs; in setCallerSaved()
399 Defs |= AllocSet.flip(); in setUnallocatableRegs()
428 Defs |= NewDefs; in update()
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H A DMicroMipsDSPInstrInfo.td189 "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
191 "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
193 "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
227 Defs<[DSPOutFlag22]>;
230 Defs<[DSPOutFlag22]>;
233 Defs<[DSPOutFlag22]>;
236 Defs<[DSPOutFlag22]>;
261 "shllv.ph", int_mips_shll_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
264 Defs<[DSPOutFlag22]>;
266 "shllv.qb", int_mips_shll_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag22]>;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
106 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
152 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
209 Defs.clear(); in InsertITInstructions()
211 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
262 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
76 Defs.insert(V); in findAllDefs()
84 if (Defs.insert(Op).second) in findAllDefs()
87 return Defs; in findAllDefs()
222 auto Defs = findAllDefs(U); in runOnUse() local
225 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); })) in runOnUse()
231 for (Value *V : Defs) in runOnUse()
236 for (Value *V : Defs) in runOnUse()
247 for (Value *V : Defs) in runOnUse()
/netbsd-src/external/apache2/llvm/dist/clang/utils/TableGen/
H A DRISCVVEmitter.cpp241 std::vector<std::unique_ptr<RVVIntrinsic>> &Defs, raw_ostream &o,
901 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createHeader() local
902 createRVVIntrinsics(Defs); in createHeader()
957 std::stable_sort(Defs.begin(), Defs.end(), in createHeader()
964 emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) { in createHeader()
974 emitArchMacroAndBody(Defs, OS, [](raw_ostream &OS, const RVVIntrinsic &Inst) { in createHeader()
988 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createBuiltins() local
989 createRVVIntrinsics(Defs); in createBuiltins()
995 for (auto &Def : Defs) { in createBuiltins()
1007 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createCodeGen() local
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H A DNeonEmitter.cpp548 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
550 SmallVectorImpl<Intrinsic *> &Defs);
552 SmallVectorImpl<Intrinsic *> &Defs);
1994 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef() argument
2001 for (auto *Def : Defs) { in genBuiltinsDef()
2021 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode() argument
2035 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2100 SmallVectorImpl<Intrinsic *> &Defs) { in genIntrinsicRangeCheckCode() argument
2105 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2190 SmallVector<Intrinsic *, 128> Defs; in runHeader() local
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H A DSveEmitter.cpp1230 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createHeader() local
1233 createIntrinsic(R, Defs); in createHeader()
1240 Defs.begin(), Defs.end(), [](const std::unique_ptr<Intrinsic> &A, in createHeader()
1249 for (auto &I : Defs) { in createHeader()
1291 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createBuiltins() local
1293 createIntrinsic(R, Defs); in createBuiltins()
1296 llvm::sort(Defs, [](const std::unique_ptr<Intrinsic> &A, in createBuiltins()
1302 for (auto &Def : Defs) { in createBuiltins()
1322 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createCodeGenMap() local
1324 createIntrinsic(R, Defs); in createCodeGenMap()
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H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local
9 for (const auto &Entry : Defs) { in EmitClangDataCollectors()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DLiveVariables.cpp442 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
481 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
485 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
486 while (!Defs.empty()) { in UpdatePhysRegDefs()
487 Register Reg = Defs.back(); in UpdatePhysRegDefs()
488 Defs.pop_back(); in UpdatePhysRegDefs()
499 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
557 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
559 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
564 SmallVector<unsigned, 4> Defs; in runOnBlock() local
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H A DReachingDefAnalysis.cpp397 InstSet &Defs) const { in getGlobalReachingDefs()
399 Defs.insert(Def); in getGlobalReachingDefs()
404 getLiveOuts(MBB, PhysReg, Defs); in getGlobalReachingDefs()
408 MCRegister PhysReg, InstSet &Defs) const { in getLiveOuts()
410 getLiveOuts(MBB, PhysReg, Defs, VisitedBBs); in getLiveOuts()
414 MCRegister PhysReg, InstSet &Defs, in getLiveOuts() argument
426 Defs.insert(Def); in getLiveOuts()
429 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); in getLiveOuts()
556 SmallSet<int, 2> Defs; in isSafeToMove() local
562 Defs.insert(MO.getReg()); in isSafeToMove()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp44 Defs[Hexagon::SA0].insert(Unconditional); // FIXME: define or change SA0? in init()
45 Defs[Hexagon::LC0].insert(Unconditional); in init()
48 Defs[Hexagon::SA1].insert(Unconditional); // FIXME: define or change SA0? in init()
49 Defs[Hexagon::LC1].insert(Unconditional); in init()
127 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
394 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates()
407 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
506 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly() local
507 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp155 auto *Defs = MSSA->getWritableBlockDefs(MA->getBlock()); in getPreviousDefInBlock() local
158 if (Defs) { in getPreviousDefInBlock()
163 if (Iter != Defs->rend()) in getPreviousDefInBlock()
182 auto *Defs = MSSA->getWritableBlockDefs(BB); in getPreviousDefFromEnd() local
184 if (Defs) { in getPreviousDefFromEnd()
185 CachedPreviousDef.insert({BB, &*Defs->rbegin()}); in getPreviousDefFromEnd()
186 return &*Defs->rbegin(); in getPreviousDefFromEnd()
263 auto *Defs = MSSA->getBlockDefs(MU->getBlock()); in insertUse() local
264 (void)Defs; in insertUse()
265 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrKL.td20 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
27 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
33 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
40 Defs = [EFLAGS] in {
70 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86InstrArithmetic.td56 // AL is really implied by AX, but the registers in Defs must match the
59 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
67 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
72 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
78 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
84 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
94 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
98 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
102 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
110 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
[all …]
H A DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
81 let Defs = [AL], Uses = [DX] in
83 let Defs = [AX], Uses = [DX] in
86 let Defs = [EAX], Uses = [DX] in
90 let Defs = [AL] in
93 let Defs = [AX] in
96 let Defs = [EAX] in
427 let Defs = [EAX, EDX], Uses = [ECX] in
430 let Defs = [RAX, RDX], Uses = [ECX] in
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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DCTagsEmitter.cpp66 const auto &Defs = Records.getDefs(); in run() local
69 Tags.reserve(Classes.size() + Defs.size()); in run()
72 for (const auto &D : Defs) in run()

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