| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 91 SmallVector<MCRegister, 4> DefRegs; member
126 RegsToInvalidate.insert(I->second.DefRegs.begin(), in invalidateRegister()
127 I->second.DefRegs.end()); in invalidateRegister()
142 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister()
169 if (!is_contained(Copy.DefRegs, Def)) in trackCopy()
170 Copy.DefRegs.push_back(Def); in trackCopy()
194 if (CI->second.DefRegs.size() != 1) in findCopyDefViaUnit()
196 MCRegUnitIterator RUI(CI->second.DefRegs[0], &TRI); in findCopyDefViaUnit()
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| H A D | LiveVariables.cpp | 511 SmallVector<unsigned, 4> DefRegs; in runOnInstr() local
533 DefRegs.push_back(MOReg); in runOnInstr()
552 for (unsigned i = 0, e = DefRegs.size(); i != e; ++i) { in runOnInstr()
553 unsigned MOReg = DefRegs[i]; in runOnInstr()
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| H A D | MachineOutliner.cpp | 789 SmallSet<Register, 2> UseRegs, DefRegs; in outline() local
808 DefRegs.insert(MOP.getReg()); in outline()
823 for (const Register &I : DefRegs) in outline()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1212 SmallVector<Register, 16> DefRegs(OpdMapper.getVRegs(0)); in applyMappingLoad() local
2160 SmallVector<Register, 1> DefRegs(OpdMapper.getVRegs(0)); in applyMappingImpl() local
2161 if (DefRegs.empty()) in applyMappingImpl()
2162 DefRegs.push_back(DstReg); in applyMappingImpl()
2163 B.buildTrunc(DefRegs[0], NewDstReg); in applyMappingImpl()
2194 SmallVector<Register, 2> DefRegs(OpdMapper.getVRegs(0)); in applyMappingImpl() local
2199 if (DefRegs.empty()) { in applyMappingImpl()
2215 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
2217 B.buildSelect(DefRegs[0], CondRegs[0], Src1Regs[0], Src2Regs[0]); in applyMappingImpl()
2218 B.buildSelect(DefRegs[1], CondRegs[0], Src1Regs[1], Src2Regs[1]); in applyMappingImpl()
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 470 std::set<RegisterRef> DefRegs; in updateDeadsInRange() local
480 DefRegs.insert(Op); in updateDeadsInRange()
500 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
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| H A D | HexagonConstPropagation.cpp | 2848 SmallVector<unsigned,2> DefRegs; in rewriteHexConstDefs() local
2857 DefRegs.push_back(R); in rewriteHexConstDefs()
2870 for (unsigned i = 0, n = DefRegs.size(); i < n; ++i) { in rewriteHexConstDefs()
2871 unsigned R = DefRegs[i]; in rewriteHexConstDefs()
2962 AllDefs = (ChangedNum == DefRegs.size()); in rewriteHexConstDefs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1676 list<Register> DefRegs> :
1680 let Defs = DefRegs;
1712 list<Register> DefRegs> :
1715 let Defs = DefRegs;
1736 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1739 let Defs = DefRegs;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2429 DenseMap<Register, bool> DefRegs; in emitSjLjDispatchBlock() local
2432 DefRegs[MOp.getReg()] = true; in emitSjLjDispatchBlock()
2437 if (!DefRegs[Reg]) in emitSjLjDispatchBlock()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 10550 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
10555 DefRegs[OI->getReg()] = true; in EmitSjLjDispatchBlock()
10570 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 34005 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
34008 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
34013 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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