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Searched refs:DefReg (Results 1 – 25 of 32) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DDetectDeadLanes.cpp250 Register DefReg = Def.getReg(); in transferUsedLanes() local
251 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in transferUsedLanes()
285 Register DefReg = Def.getReg(); in transferDefinedLanesStep() local
286 if (!Register::isVirtualRegister(DefReg)) in transferDefinedLanesStep()
288 unsigned DefRegIdx = Register::virtReg2Index(DefReg); in transferDefinedLanesStep()
428 Register DefReg = Def.getReg(); in determineInitialUsedLanes() local
431 if (Register::isVirtualRegister(DefReg)) { in determineInitialUsedLanes()
435 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg); in determineInitialUsedLanes()
470 Register DefReg = Def.getReg(); in isUndefInput() local
471 if (!Register::isVirtualRegister(DefReg)) in isUndefInput()
[all …]
H A DTailDuplicator.cpp352 Register DefReg = MI->getOperand(0).getReg(); in processPHI() local
357 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in processPHI()
358 LocalVRMap.insert(std::make_pair(DefReg, RegSubRegPair(SrcReg, SrcSubReg))); in processPHI()
364 if (isDefLiveOut(DefReg, TailBB, MRI) || RegsUsedByPhi.count(DefReg)) in processPHI()
365 addSSAUpdateEntry(DefReg, NewDef, PredBB); in processPHI()
H A DImplicitNullChecks.cpp718 unsigned DefReg = NoRegister; in insertFaultingInstr() local
720 DefReg = MI->getOperand(0).getReg(); in insertFaultingInstr()
731 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg) in insertFaultingInstr()
H A DLiveVariables.cpp216 Register DefReg = MO.getReg(); in FindLastPartialDef() local
217 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
218 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
H A DTargetInstrInfo.cpp926 Register DefReg = MI.getOperand(0).getReg(); in isReallyTriviallyReMaterializableGeneric() local
932 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() && in isReallyTriviallyReMaterializableGeneric()
933 MI.readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
984 if (MO.isDef() && Reg != DefReg) in isReallyTriviallyReMaterializableGeneric()
H A DPHIElimination.cpp203 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction() local
204 if (MRI->use_nodbg_empty(DefReg)) { in runOnMachineFunction()
H A DMachineSink.cpp1606 for (auto DefReg : DefedRegsInCopy) { in getSingleLiveInSuccBB() local
1608 getSingleLiveInSuccBB(CurBB, SinkableBBs, DefReg, TRI); in getSingleLiveInSuccBB()
1641 for (unsigned DefReg : DefedRegsInCopy) in updateLiveIn() local
1642 for (MCSubRegIterator S(DefReg, TRI, true); S.isValid(); ++S) in updateLiveIn()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp469 Register DefReg = MO.getReg(); in oneUseDominatesOtherUses() local
470 if (!Register::isVirtualRegister(DefReg) || in oneUseDominatesOtherUses()
471 !MFI.isVRegStackified(DefReg)) in oneUseDominatesOtherUses()
473 assert(MRI.hasOneNonDBGUse(DefReg)); in oneUseDominatesOtherUses()
474 const MachineOperand &NewUse = *MRI.use_nodbg_begin(DefReg); in oneUseDominatesOtherUses()
641 Register DefReg = MRI.createVirtualRegister(RegClass); in moveAndTeeForMultiUse() local
646 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
648 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
664 LIS.createAndComputeVirtRegInterval(DefReg); in moveAndTeeForMultiUse()
665 MFI.stackifyVReg(MRI, DefReg); in moveAndTeeForMultiUse()
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H A DWebAssemblyExplicitLocals.cpp192 for (auto DefReg : Def->defs()) { in findStartOfTree() local
193 if (!MFI.isVRegStackified(DefReg.getReg())) { in findStartOfTree()
H A DWebAssemblyCFGStackify.cpp851 Register DefReg = MI.getOperand(2).getReg(); in unstackifyVRegsUsedInSplitBB() local
854 MFI.unstackifyVReg(DefReg); in unstackifyVRegsUsedInSplitBB()
855 unsigned CopyOpc = getCopyOpcode(MRI.getRegClass(DefReg)); in unstackifyVRegsUsedInSplitBB()
857 .addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
858 BuildMI(MBB, &MI, MI.getDebugLoc(), TII.get(CopyOpc), Reg).addReg(DefReg); in unstackifyVRegsUsedInSplitBB()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp508 const Register DefReg = I.getOperand(0).getReg(); in selectLoadStoreOp() local
509 LLT Ty = MRI.getType(DefReg); in selectLoadStoreOp()
510 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
546 addFullAddress(MIB, AM).addUse(DefReg); in selectLoadStoreOp()
568 const Register DefReg = I.getOperand(0).getReg(); in selectFrameIndexOrGep() local
569 LLT Ty = MRI.getType(DefReg); in selectFrameIndexOrGep()
621 const Register DefReg = I.getOperand(0).getReg(); in selectGlobalValue() local
622 LLT Ty = MRI.getType(DefReg); in selectGlobalValue()
640 const Register DefReg = I.getOperand(0).getReg(); in selectConstant() local
641 LLT Ty = MRI.getType(DefReg); in selectConstant()
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H A DX86DomainReassignment.cpp592 Register DefReg = DefOp.getReg(); in buildClosure() local
593 if (!DefReg.isVirtual()) { in buildClosure()
597 visitRegister(C, DefReg, Domain, Worklist); in buildClosure()
H A DX86LoadValueInjectionLoadHardening.cpp370 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph() local
371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) { in getGadgetGraph()
376 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()
H A DX86SpeculativeLoadHardening.cpp1786 Register DefReg = MI.getOperand(0).getReg(); in sinkPostLoadHardenedInst() local
1792 for (MachineInstr &UseMI : MRI->use_instructions(DefReg)) { in sinkPostLoadHardenedInst()
1817 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) || in sinkPostLoadHardenedInst()
1818 (IndexMO.isReg() && IndexMO.getReg() == DefReg)) in sinkPostLoadHardenedInst()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64RedundantCopyElimination.cpp382 Register DefReg = MI->getOperand(0).getReg(); in optimizeBlock() local
385 if (!MRI->isReserved(DefReg) && in optimizeBlock()
389 if (KnownReg.Reg != DefReg && in optimizeBlock()
390 !TRI->isSuperRegister(DefReg, KnownReg.Reg)) in optimizeBlock()
414 if (TRI->isSuperRegister(DefReg, KnownReg.Reg) && KnownReg.Imm < 0) in optimizeBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h397 Register DefReg = MI.getOperand(I).getReg(); in tryFoldUnmergeCast() local
398 UpdatedDefs.push_back(DefReg); in tryFoldUnmergeCast()
399 Builder.buildTrunc(DefReg, NewUnmerge.getReg(I)); in tryFoldUnmergeCast()
688 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineUnmergeValues() local
689 Builder.buildMerge(DefReg, Regs); in tryCombineUnmergeValues()
690 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
704 Register DefReg = MI.getOperand(Idx).getReg(); in tryCombineUnmergeValues() local
705 Builder.buildInstr(ConvertOp, {DefReg}, {MergeSrc}); in tryCombineUnmergeValues()
706 UpdatedDefs.push_back(DefReg); in tryCombineUnmergeValues()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp671 Register DefReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
677 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
724 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
743 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in recordUnoptimizableWebs()
783 Register DefReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
785 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { in markSwapsForRemoval()
H A DPPCPreEmitPeephole.cpp253 Register DefReg; in addLinkerOpt() member
285 if (!BBI->readsRegister(Pair.DefReg, TRI) && in addLinkerOpt()
286 !BBI->modifiesRegister(Pair.DefReg, TRI)) in addLinkerOpt()
295 if (UseOp && UseOp->isReg() && UseOp->getReg() == Pair.DefReg && in addLinkerOpt()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips16InstrInfo.cpp369 int DefReg = 0; in loadImmediate() local
373 DefReg = MO.getReg(); in loadImmediate()
392 if (DefReg != Reg) { in loadImmediate()
407 if (DefReg!= SpReg) { in loadImmediate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp248 MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
270 MachineInstr *emitCSetForICMP(Register DefReg, unsigned Pred,
2109 Register DefReg = I.getOperand(0).getReg(); in earlySelect() local
2110 LLT Ty = MRI.getType(DefReg); in earlySelect()
2113 RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass, MRI); in earlySelect()
2116 RBI.constrainGenericRegister(DefReg, AArch64::GPR32RegClass, MRI); in earlySelect()
2189 const Register DefReg = I.getOperand(0).getReg(); in select() local
2190 const LLT DefTy = MRI.getType(DefReg); in select()
2193 MRI.getRegClassOrRegBank(DefReg); in select()
2212 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFoldOperands.cpp1658 Register DefReg = Def.getReg(); in tryFoldLoad() local
1660 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
1665 for (const MachineInstr &I : MRI->use_nodbg_instructions(DefReg)) { in tryFoldLoad()
1685 const TargetRegisterClass *RC = MRI->getRegClass(DefReg); in tryFoldLoad()
1686 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1688 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp178 static bool isRegUsedByPhiNodes(Register DefReg, in isRegUsedByPhiNodes() argument
181 if (P.second == DefReg) in isRegUsedByPhiNodes()
202 Register DefReg = findLocalRegDef(LocalMI); in flushLocalValueMap() local
203 if (!DefReg) in flushLocalValueMap()
205 if (FuncInfo.RegsWithFixups.count(DefReg)) in flushLocalValueMap()
207 bool UsedByPHI = isRegUsedByPhiNodes(DefReg, FuncInfo); in flushLocalValueMap()
208 if (!UsedByPHI && MRI.use_nodbg_empty(DefReg)) { in flushLocalValueMap()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp1039 unsigned DefReg = 0; in getUniqueDefVReg() local
1046 if (DefReg != 0) in getUniqueDefVReg()
1048 DefReg = R; in getUniqueDefVReg()
1050 return DefReg; in getUniqueDefVReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp215 Register DefReg = MODef.getReg(); in eraseInstrWithNoUses() local
216 if (!Register::isVirtualRegister(DefReg)) { in eraseInstrWithNoUses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp204 for (Register DefReg : NewVRegs) in repairReg() local
205 UnMergeBuilder.addDef(DefReg); in repairReg()

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