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Searched refs:DefRC (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp382 const TargetRegisterClass *DefRC, in shareSameRegisterFile() argument
387 if (DefRC == SrcRC) in shareSameRegisterFile()
393 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
401 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
406 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
409 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
412 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
417 return shareSameRegisterFile(*this, DefRC, DefSubReg, SrcRC, SrcSubReg); in shouldRewriteCopySrc()
H A DDetectDeadLanes.cpp370 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in determineInitialDefinedLanes() local
384 } else if (isCrossCopy(*MRI, DefMI, DefRC, MO)) { in determineInitialDefinedLanes()
H A DPeepholeOptimizer.cpp674 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg); in findNextSource() local
737 if (!TRI->shouldRewriteCopySrc(DefRC, RegSubReg.SubReg, SrcRC, in findNextSource()
1237 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg); in rewriteSource() local
1238 Register NewVReg = MRI->createVirtualRegister(DefRC); in rewriteSource()
H A DRegisterCoalescer.cpp1310 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF); in reMaterializeTrivialDef() local
1322 if (!DefRC->contains(NewDstReg)) in reMaterializeTrivialDef()
1353 TRI->getCommonSubClass(DefRC, DstRC); in reMaterializeTrivialDef()
1402 if (DefRC != nullptr) { in reMaterializeTrivialDef()
1404 NewRC = TRI->getMatchingSuperRegClass(NewRC, DefRC, NewIdx); in reMaterializeTrivialDef()
1406 NewRC = TRI->getCommonSubClass(NewRC, DefRC); in reMaterializeTrivialDef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterInfo.h73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
H A DX86RegisterInfo.cpp215 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
222 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && in shouldRewriteCopySrc()
226 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
H A DX86SpeculativeLoadHardening.cpp1967 auto *DefRC = MRI->getRegClass(OldDefReg); in hardenPostLoad() local
1972 Register UnhardenedReg = MRI->createVirtualRegister(DefRC); in hardenPostLoad()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp429 const TargetRegisterClass *DefRC = nullptr; in select() local
431 DefRC = TRI.getRegClass(DestReg); in select()
433 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
436 return RBI.constrainGenericRegister(DestReg, *DefRC, MRI); in select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp913 bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
918 if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 && in shouldRewriteCopySrc()
923 return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg, in shouldRewriteCopySrc()
H A DARMBaseRegisterInfo.h213 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h208 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
H A DAMDGPUInstructionSelector.cpp210 const TargetRegisterClass *DefRC in selectPHI() local
212 if (!DefRC) { in selectPHI()
219 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI); in selectPHI()
220 if (!DefRC) { in selectPHI()
228 return RBI.constrainGenericRegister(DefReg, *DefRC, *MRI); in selectPHI()
H A DSIRegisterInfo.cpp2172 const TargetRegisterClass *DefRC, in shouldRewriteCopySrc() argument
2192 return getCommonSubClass(DefRC, SrcRC) != nullptr; in shouldRewriteCopySrc()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h593 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1959 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg); in evaluate() local
1960 unsigned SubLo = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_lo); in evaluate()
1961 unsigned SubHi = HRI.getHexagonSubRegIndex(DefRC, Hexagon::ps_sub_hi); in evaluate()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp2195 const TargetRegisterClass *DefRC in select() local
2197 if (!DefRC) { in select()
2203 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
2204 if (!DefRC) { in select()
2212 return RBI.constrainGenericRegister(DefReg, *DefRC, MRI); in select()