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Searched refs:DefMI (Results 1 – 25 of 66) sorted by relevance

123

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
96 if (DefMI->getParent() != MBB) in getAccDefMI()
98 if (DefMI->isCopyLike()) { in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
113 return DefMI; in getAccDefMI()
146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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H A DARMHazardRecognizer.cpp26 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
37 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
52 MachineInstr *DefMI = LastMI; in getHazardType() local
65 DefMI = &*I; in getHazardType()
69 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
71 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp185 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
189 return TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
194 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
198 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
213 std::max(InstrLatency, TII->defaultDefLatency(SchedModel, *DefMI)); in computeOperandLatency()
217 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
241 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() in computeOperandLatency()
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
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H A DLiveRangeEdit.cpp71 const MachineInstr *DefMI, in checkRematerializable() argument
73 assert(DefMI && "Missing instruction"); in checkRematerializable()
75 if (!TII.isTriviallyReMaterializable(*DefMI, aa)) in checkRematerializable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable() local
91 if (!DefMI) in scanRemattable()
93 checkRematerializable(OrigVNI, DefMI, aa); in scanRemattable()
187 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
193 if (DefMI && DefMI != MI) in foldAsLoad()
197 DefMI = MI; in foldAsLoad()
207 if (!DefMI || !UseMI) in foldAsLoad()
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H A DMachineTraceMetrics.cpp628 const MachineInstr *DefMI; member
632 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
633 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
641 DefMI = DefI->getParent(); in DataDep()
770 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
772 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
795 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in updateDepth()
800 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
802 if (!Dep.DefMI->isTransient()) in updateDepth()
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H A DPHIElimination.cpp166 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in runOnMachineFunction() local
167 if (!DefMI) in runOnMachineFunction()
178 MachineBasicBlock *DefMBB = DefMI->getParent(); in runOnMachineFunction()
202 for (MachineInstr *DefMI : ImpDefs) { in runOnMachineFunction()
203 Register DefReg = DefMI->getOperand(0).getReg(); in runOnMachineFunction()
206 LIS->RemoveMachineInstrFromMaps(*DefMI); in runOnMachineFunction()
207 DefMI->eraseFromParent(); in runOnMachineFunction()
474 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
475 if (DefMI->isImplicitDef()) in LowerPHINode()
476 ImpDefs.insert(DefMI); in LowerPHINode()
H A DRegisterCoalescer.cpp827 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
828 if (!DefMI) in removeCopyByCommutingDef()
830 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
834 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg()); in removeCopyByCommutingDef()
837 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
850 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
853 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
878 << *DefMI); in removeCopyByCommutingDef()
882 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
884 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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H A DTwoAddressInstructionPass.cpp206 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in getSingleDef()
207 if (DefMI.getParent() != BB || DefMI.isDebugValue()) in getSingleDef()
210 Ret = &DefMI; in getSingleDef()
211 else if (Ret != &DefMI) in getSingleDef()
333 MachineInstr *DefMI = &MI; in isKilled() local
338 if (!isPlainlyKilled(DefMI, Reg, LIS)) in isKilled()
347 DefMI = Begin->getParent(); in isKilled()
352 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
886 for (MachineInstr &DefMI : MRI->def_instructions(Reg)) { in isDefTooClose()
887 if (DefMI.getParent() != MBB || DefMI.isCopy() || DefMI.isCopyLike()) in isDefTooClose()
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H A DMachineCSE.cpp176 MachineInstr *DefMI = MRI->getVRegDef(Reg); in INITIALIZE_PASS_DEPENDENCY() local
177 if (!DefMI->isCopy()) in INITIALIZE_PASS_DEPENDENCY()
179 Register SrcReg = DefMI->getOperand(1).getReg(); in INITIALIZE_PASS_DEPENDENCY()
182 if (DefMI->getOperand(0).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
196 if (DefMI->getOperand(1).getSubReg()) in INITIALIZE_PASS_DEPENDENCY()
200 LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI); in INITIALIZE_PASS_DEPENDENCY()
211 DefMI->changeDebugValuesDefReg(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
213 DefMI->eraseFromParent(); in INITIALIZE_PASS_DEPENDENCY()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp66 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
143 MachineInstr &DefMI) { in tryToTuneBranch() argument
145 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
151 switch (DefMI.getOpcode()) { in tryToTuneBranch()
197 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
200 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
204 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
252 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
255 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
259 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting); in tryToTuneBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp352 for (auto DefMI : List) { in chooseBestLEA() local
354 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1); in chooseBestLEA()
366 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
373 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
383 BestLEA = DefMI; in chooseBestLEA()
529 MachineInstr *DefMI; in removeRedundantAddrCalc() local
532 if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist)) in removeRedundantAddrCalc()
542 DefMI->removeFromParent(); in removeRedundantAddrCalc()
543 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
544 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
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H A DX86TileConfig.cpp155 for (auto &DefMI : MRI.def_instructions(R)) { in INITIALIZE_PASS_DEPENDENCY() local
156 MachineBasicBlock &MBB = *DefMI.getParent(); in INITIALIZE_PASS_DEPENDENCY()
157 if (DefMI.isMoveImmediate()) { in INITIALIZE_PASS_DEPENDENCY()
160 assert(Imm == DefMI.getOperand(1).getImm() && in INITIALIZE_PASS_DEPENDENCY()
164 Imm = DefMI.getOperand(1).getImm(); in INITIALIZE_PASS_DEPENDENCY()
177 auto Iter = DefMI.getIterator(); in INITIALIZE_PASS_DEPENDENCY()
H A DX86PreTileConfig.cpp211 MachineInstr *DefMI = MRI->getVRegDef(R); in INITIALIZE_PASS_DEPENDENCY() local
212 assert(DefMI && "R must has one define instruction"); in INITIALIZE_PASS_DEPENDENCY()
213 MachineBasicBlock *DefMBB = DefMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
214 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second) in INITIALIZE_PASS_DEPENDENCY()
216 if (DefMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
217 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2) in INITIALIZE_PASS_DEPENDENCY()
218 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB())) in INITIALIZE_PASS_DEPENDENCY()
219 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def. in INITIALIZE_PASS_DEPENDENCY()
221 WorkList.push_back(DefMI->getOperand(I).getReg()); in INITIALIZE_PASS_DEPENDENCY()
223 RecordShape(DefMI, DefMBB); in INITIALIZE_PASS_DEPENDENCY()
H A DX86CallFrameOptimization.cpp620 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
624 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
625 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
626 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
631 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
635 return &DefMI; in canFoldIntoRegPush()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp387 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() local
388 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); in getDefSrcRegIgnoringCopies()
391 unsigned Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
393 Register SrcReg = DefMI->getOperand(1).getReg(); in getDefSrcRegIgnoringCopies()
397 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
399 Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
401 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; in getDefSrcRegIgnoringCopies()
420 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef() local
421 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
548 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp280 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
282 assert(DefMI); in isCallViaRegister()
286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
289 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
295 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
296 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
298 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp464 MachineInstr *DefMI; in eliminateTruncSeq() local
491 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
492 if (DefMI) in eliminateTruncSeq()
498 DefMI = MRI->getVRegDef(SrcReg); in eliminateTruncSeq()
500 if (!DefMI) in eliminateTruncSeq()
514 if (DefMI->isPHI()) { in eliminateTruncSeq()
517 for (unsigned i = 1, e = DefMI->getNumOperands(); i < e; i += 2) { in eliminateTruncSeq()
518 MachineOperand &opnd = DefMI->getOperand(i); in eliminateTruncSeq()
534 } else if (!TruncSizeCompatible(TruncSize, DefMI->getOpcode())) { in eliminateTruncSeq()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp518 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() local
520 if (!DefMI) in simplifyCode()
523 unsigned DefOpc = DefMI->getOpcode(); in simplifyCode()
533 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
556 unsigned DefReg1 = DefMI->getOperand(1).getReg(); in simplifyCode()
557 unsigned DefReg2 = DefMI->getOperand(2).getReg(); in simplifyCode()
558 unsigned DefImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
602 .add(DefMI->getOperand(1)); in simplifyCode()
607 (DefMI->getOperand(2).getImm() == 0 || in simplifyCode()
608 DefMI->getOperand(2).getImm() == 3)) { in simplifyCode()
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H A DPPCInstrInfo.h204 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
208 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
214 MachineInstr &DefMI) const;
218 unsigned ConstantOpNo, MachineInstr &DefMI,
233 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
238 const MachineInstr &DefMI,
243 const MachineInstr &DefMI,
316 const MachineInstr &DefMI, unsigned DefIdx,
327 const MachineInstr &DefMI, in hasLowDefLatency() argument
472 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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H A DPPCInstrInfo.cpp167 const MachineInstr &DefMI, unsigned DefIdx, in getOperandLatency() argument
170 int Latency = PPCGenInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx, in getOperandLatency()
173 if (!DefMI.getParent()) in getOperandLatency()
176 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
182 &DefMI.getParent()->getParent()->getRegInfo(); in getOperandLatency()
192 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
751 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getConstantFromConstantPool() local
752 for (auto MO2 : DefMI->uses()) in getConstantFromConstantPool()
2040 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in onlyFoldImmediate() argument
2043 unsigned DefOpc = DefMI.getOpcode(); in onlyFoldImmediate()
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H A DPPCVSXSwapRemoval.cpp618 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
619 assert(SwapMap.find(DefMI) != SwapMap.end() && in formWebs()
621 int DefIdx = SwapMap[DefMI]; in formWebs()
629 LLVM_DEBUG(DefMI->dump()); in formWebs()
723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
724 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
725 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
735 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
754 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
800 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
499 bool Invert = !DefMI; in optimizeSelect()
500 if (!DefMI) in optimizeSelect()
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
502 if (!DefMI) in optimizeSelect()
514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
517 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
520 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
538 SeenMIs.erase(DefMI); in optimizeSelect()
544 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIFixSGPRCopies.cpp625 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction() local
630 if (isSafeToFoldImmIntoCopy(&MI, DefMI, TII, SMovOp, Imm)) { in runOnMachineFunction()
736 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in runOnMachineFunction() local
737 if (DefMI && TII->isFoldableCopy(*DefMI)) { in runOnMachineFunction()
738 const MachineOperand &Def = DefMI->getOperand(0); in runOnMachineFunction()
742 const MachineOperand &Copied = DefMI->getOperand(1); in runOnMachineFunction()
827 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode() local
828 if (DefMI && DefMI->isPHI()) in processPHINode()
829 PHIOperands.insert(DefMI); in processPHINode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp546 bool VEInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in FoldImmediate() argument
552 switch (DefMI.getOpcode()) { in FoldImmediate()
558 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
560 assert(DefMI.getOperand(1).isImm()); in FoldImmediate()
561 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
563 DefMI.getOperand(1).getImm() + mimm2Val(DefMI.getOperand(2).getImm()); in FoldImmediate()
569 LLVM_DEBUG(DefMI.dump()); in FoldImmediate()
571 assert(DefMI.getOperand(2).isImm()); in FoldImmediate()
572 if (!DefMI.getOperand(3).isImm()) in FoldImmediate()
575 ImmVal = DefMI.getOperand(2).getImm() + DefMI.getOperand(3).getImm(); in FoldImmediate()
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h324 if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, in tryFoldImplicitDef() local
347 markInstAndDefDead(MI, *DefMI, DeadInsts); in tryFoldImplicitDef()
910 void markDefDead(MachineInstr &MI, MachineInstr &DefMI,
923 while (PrevMI != &DefMI) {
928 if (TmpDef != &DefMI) {
940 if (PrevMI == &DefMI) {
943 for (MachineOperand &Def : DefMI.defs()) {
950 if (!MRI.hasOneUse(DefMI.getOperand(DefIdx).getReg()))
958 DeadInsts.push_back(&DefMI);
967 void markInstAndDefDead(MachineInstr &MI, MachineInstr &DefMI,
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