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Searched refs:DefIdx (Results 1 – 25 of 42) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCInstrItineraries.h184 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding() argument
188 if ((FirstDefIdx + DefIdx) >= LastDefIdx) in hasPipelineForwarding()
190 if (Forwardings[FirstDefIdx + DefIdx] == 0) in hasPipelineForwarding()
198 return Forwardings[FirstDefIdx + DefIdx] == in hasPipelineForwarding()
205 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency() argument
210 int DefCycle = getOperandCycle(DefClass, DefIdx); in getOperandLatency()
220 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
H A DMCSubtargetInfo.h176 unsigned DefIdx) const { in getWriteLatencyEntry() argument
177 assert(DefIdx < SC->NumWriteLatencyEntries && in getWriteLatencyEntry()
180 return &WriteLatencyTable[SC->WriteLatencyIdx + DefIdx]; in getWriteLatencyEntry()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetSchedule.cpp158 unsigned DefIdx = 0; in findDefIdx() local
162 ++DefIdx; in findDefIdx()
164 return DefIdx; in findDefIdx()
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
219 if (DefIdx < SCDesc->NumWriteLatencyEntries) { in computeOperandLatency()
222 STI->getWriteLatencyEntry(SCDesc, DefIdx); in computeOperandLatency()
244 errs() << "DefIdx " << DefIdx << " exceeds machine model writes for " in computeOperandLatency()
H A DLiveIntervalCalc.cpp45 SlotIndex DefIdx = in createDeadDef() local
49 LR.createDeadDef(DefIdx, Alloc); in createDeadDef()
190 unsigned DefIdx; in extendToUses() local
193 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) { in extendToUses()
196 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber(); in extendToUses()
H A DTargetInstrInfo.cpp1090 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
1100 return ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
1102 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1164 unsigned DefIdx) const { in hasLowDefLatency()
1170 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in hasLowDefLatency()
1259 unsigned DefIdx, in getOperandLatency() argument
1264 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
1284 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1290 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1294 assert(DefIdx == 0 && "REG_SEQUENCE only has one def"); in getRegSequenceInputs()
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H A DPeepholeOptimizer.cpp373 unsigned DefIdx = 0; member in __anonbcd030b40111::ValueTracker
427 DefIdx = MRI.def_begin(Reg).getOperandNo(); in ValueTracker()
1818 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg) in getNextSourceFromCopy()
1839 const MachineOperand DefOp = Def->getOperand(DefIdx); in getNextSourceFromBitcast()
1846 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; in getNextSourceFromBitcast()
1883 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromRegSequence()
1906 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs)) in getNextSourceFromRegSequence()
1927 if (Def->getOperand(DefIdx).getSubReg()) in getNextSourceFromInsertSubreg()
1940 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg)) in getNextSourceFromInsertSubreg()
1956 const MachineOperand &MODef = Def->getOperand(DefIdx); in getNextSourceFromInsertSubreg()
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H A DLiveRangeEdit.cpp149 SlotIndex DefIdx; in canRematerializeAt() local
151 DefIdx = LIS.getInstructionIndex(*RM.OrigMI); in canRematerializeAt()
158 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
H A DMachineVerifier.cpp248 SlotIndex DefIdx, const LiveRange &LR,
1882 unsigned DefIdx; in visitMachineOperand() local
1885 MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) && in visitMachineOperand()
1886 Reg != MI->getOperand(DefIdx).getReg()) in visitMachineOperand()
2114 unsigned MONum, SlotIndex DefIdx, in checkLivenessAtDef() argument
2119 if (const VNInfo *VNI = LR.getVNInfoAt(DefIdx)) { in checkLivenessAtDef()
2121 if (VNI->def != DefIdx) { in checkLivenessAtDef()
2128 report_context(DefIdx); in checkLivenessAtDef()
2136 report_context(DefIdx); in checkLivenessAtDef()
2140 LiveQueryResult LRQ = LR.Query(DefIdx); in checkLivenessAtDef()
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H A DMachineInstr.cpp289 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
290 if (DefIdx != -1) in addOperand()
291 tieOperands(DefIdx, OpNo); in addOperand()
895 unsigned DefIdx; in getRegClassConstraint() local
896 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
897 OpIdx = DefIdx; in getRegClassConstraint()
1099 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1100 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands()
1107 if (DefIdx < TiedMax) in tieOperands()
1108 UseMO.TiedTo = DefIdx + 1; in tieOperands()
H A DRenameIndependentSubregs.cpp335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
336 SlotIndex RegDefIdx = DefIdx.getRegSlot(); in computeMainRangesFixFlags()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h525 unsigned DefIdx = 0; in getDefIndex() local
529 ++DefIdx; in getDefIndex()
532 return DefIdx; in getDefIndex()
629 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineUnmergeValues() local
630 ++j, ++DefIdx) in tryCombineUnmergeValues()
631 DstRegs.push_back(MI.getOperand(DefIdx).getReg()); in tryCombineUnmergeValues()
682 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineUnmergeValues() local
684 for (unsigned j = 0, Idx = NumRegs * DefIdx + 1; j < NumRegs; in tryCombineUnmergeValues()
688 Register DefReg = MI.getOperand(DefIdx).getReg(); in tryCombineUnmergeValues()
912 unsigned DefIdx = 0) {
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
44 DefIdx != DefEnd; ++DefIdx) { in computeInstrLatency()
47 STI.getWriteLatencyEntry(&SCDesc, DefIdx); in computeInstrLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h61 const MachineInstr &MI, unsigned DefIdx,
74 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
320 const MachineInstr &DefMI, unsigned DefIdx,
324 SDNode *DefNode, unsigned DefIdx,
424 unsigned DefIdx, unsigned DefAlign) const;
428 unsigned DefIdx, unsigned DefAlign) const;
439 unsigned DefIdx, unsigned DefAlign,
444 const MachineInstr &DefMI, unsigned DefIdx,
461 const MachineInstr &DefMI, unsigned DefIdx,
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H A DARMBaseInstrInfo.cpp3844 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle() argument
3845 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getVLDMDefCycle()
3848 return ItinData->getOperandCycle(DefClass, DefIdx); in getVLDMDefCycle()
3885 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle() argument
3886 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; in getLDMDefCycle()
3889 return ItinData->getOperandCycle(DefClass, DefIdx); in getLDMDefCycle()
3988 unsigned DefIdx, unsigned DefAlign, in getOperandLatency() argument
3994 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
3995 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
4004 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); in getOperandLatency()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp621 int DefIdx = SwapMap[DefMI]; in formWebs() local
622 (void)EC->unionSets(SwapVector[DefIdx].VSEId, in formWebs()
626 SwapVector[DefIdx].VSEId, in formWebs()
725 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
727 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
728 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
734 LLVM_DEBUG(dbgs() << " def " << DefIdx << ": "); in recordUnoptimizableWebs()
801 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
802 SwapVector[DefIdx].WillRemove = 1; in markSwapsForRemoval()
H A DPPCInstrInfo.h316 const MachineInstr &DefMI, unsigned DefIdx,
320 SDNode *DefNode, unsigned DefIdx, in getOperandLatency() argument
322 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, in getOperandLatency()
328 unsigned DefIdx) const override { in hasLowDefLatency() argument
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h509 getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx,
527 bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx,
547 bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx,
1223 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs() argument
1237 unsigned DefIdx, in getExtractSubregLikeInputs() argument
1251 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs() argument
1582 SDNode *DefNode, unsigned DefIdx,
1594 const MachineInstr &DefMI, unsigned DefIdx,
1627 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency() argument
1637 unsigned DefIdx) const;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp477 unsigned DefIdx = N->getOperand(i).getResNo(); in AddSchedEdges() local
512 ST.adjustSchedDependency(OpSU, DefIdx, SU, i, Dep); in AddSchedEdges()
575 DefIdx = 0; in InitNodeNumDefs()
581 : SchedDAG(SD), Node(SU->getNode()), DefIdx(0), NodeNumDefs(0) { in RegDefIter()
589 for (;DefIdx < NodeNumDefs; ++DefIdx) { in Advance()
590 if (!Node->hasAnyUseOfValue(DefIdx)) in Advance()
592 ValueType = Node->getSimpleValueType(DefIdx); in Advance()
593 ++DefIdx; in Advance()
655 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
659 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx); in computeOperandLatency()
H A DScheduleDAGSDNodes.h141 unsigned DefIdx; variable
160 return DefIdx-1; in GetIdx()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp403 int DefIdx = mapRegToGPRIndex(MI.getOperand(0).getReg()); in handleADRP() local
406 if (DefIdx != OpIdx && (DefInfo.OneUser || DefInfo.MultiUsers)) in handleADRP()
573 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
575 if (DefIdx >= 0 && OpIdx >= 0 && in runOnMachineFunction()
576 handleMiddleInst(MI, LOHInfos[DefIdx], LOHInfos[OpIdx])) in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp218 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
219 DefIdx != DefEnd; ++DefIdx) { in getLatency()
222 DefIdx); in getLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp204 unsigned DefIdx = 0; in tryInlineAsm() local
208 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx)) in tryInlineAsm()
209 IsTiedToChangedOp = OpChanged[DefIdx]; in tryInlineAsm()
295 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx); in tryInlineAsm()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp495 int DefIdx = -1; in restoreLatency() local
507 DefIdx = OpNum; in restoreLatency()
510 assert(DefIdx >= 0 && "Def Reg not found in Src MI"); in restoreLatency()
517 DefIdx, *DstI, OpNum)); in restoreLatency()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp435 unsigned DefIdx = OpInfo.getMatchedOperand(); in lowerInlineAsm() local
438 for (unsigned i = 0; i < DefIdx; ++i) in lowerInlineAsm()
472 unsigned Flag = InlineAsm::getFlagWordForMatchingOp(UseFlag, DefIdx); in lowerInlineAsm()
H A DUtils.cpp172 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands() local
173 if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx)) in constrainSelectedInstRegOperands()
174 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()

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