1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "MCTargetDesc/PPCMCTargetDesc.h"
10 #include "TargetInfo/PowerPCTargetInfo.h"
11 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
12 #include "llvm/MC/MCFixedLenDisassembler.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/Support/Endian.h"
16 #include "llvm/Support/TargetRegistry.h"
17
18 using namespace llvm;
19
20 DEFINE_PPC_REGCLASSES;
21
22 #define DEBUG_TYPE "ppc-disassembler"
23
24 typedef MCDisassembler::DecodeStatus DecodeStatus;
25
26 namespace {
27 class PPCDisassembler : public MCDisassembler {
28 bool IsLittleEndian;
29
30 public:
PPCDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool IsLittleEndian)31 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32 bool IsLittleEndian)
33 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34
35 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36 ArrayRef<uint8_t> Bytes, uint64_t Address,
37 raw_ostream &CStream) const override;
38 };
39 } // end anonymous namespace
40
createPPCDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)41 static MCDisassembler *createPPCDisassembler(const Target &T,
42 const MCSubtargetInfo &STI,
43 MCContext &Ctx) {
44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45 }
46
createPPCLEDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)47 static MCDisassembler *createPPCLEDisassembler(const Target &T,
48 const MCSubtargetInfo &STI,
49 MCContext &Ctx) {
50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51 }
52
LLVMInitializePowerPCDisassembler()53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
54 // Register the disassembler for each target.
55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
56 createPPCDisassembler);
57 TargetRegistry::RegisterMCDisassembler(getThePPC32LETarget(),
58 createPPCLEDisassembler);
59 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
60 createPPCDisassembler);
61 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
62 createPPCLEDisassembler);
63 }
64
decodeCondBrTarget(MCInst & Inst,unsigned Imm,uint64_t,const void *)65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
66 uint64_t /*Address*/,
67 const void * /*Decoder*/) {
68 Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
69 return MCDisassembler::Success;
70 }
71
decodeDirectBrTarget(MCInst & Inst,unsigned Imm,uint64_t,const void *)72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
73 uint64_t /*Address*/,
74 const void * /*Decoder*/) {
75 int32_t Offset = SignExtend32<24>(Imm);
76 Inst.addOperand(MCOperand::createImm(Offset));
77 return MCDisassembler::Success;
78 }
79
80 // FIXME: These can be generated by TableGen from the existing register
81 // encoding values!
82
83 template <std::size_t N>
decodeRegisterClass(MCInst & Inst,uint64_t RegNo,const MCPhysReg (& Regs)[N])84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
85 const MCPhysReg (&Regs)[N]) {
86 assert(RegNo < N && "Invalid register number");
87 Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
88 return MCDisassembler::Success;
89 }
90
DecodeCRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)91 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
92 uint64_t Address,
93 const void *Decoder) {
94 return decodeRegisterClass(Inst, RegNo, CRRegs);
95 }
96
DecodeCRBITRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)97 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
98 uint64_t Address,
99 const void *Decoder) {
100 return decodeRegisterClass(Inst, RegNo, CRBITRegs);
101 }
102
DecodeF4RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)103 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
104 uint64_t Address,
105 const void *Decoder) {
106 return decodeRegisterClass(Inst, RegNo, FRegs);
107 }
108
DecodeF8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)109 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
110 uint64_t Address,
111 const void *Decoder) {
112 return decodeRegisterClass(Inst, RegNo, FRegs);
113 }
114
DecodeVFRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)115 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
116 uint64_t Address,
117 const void *Decoder) {
118 return decodeRegisterClass(Inst, RegNo, VFRegs);
119 }
120
DecodeVRRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)121 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
122 uint64_t Address,
123 const void *Decoder) {
124 return decodeRegisterClass(Inst, RegNo, VRegs);
125 }
126
DecodeVSRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)127 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
128 uint64_t Address,
129 const void *Decoder) {
130 return decodeRegisterClass(Inst, RegNo, VSRegs);
131 }
132
DecodeVSFRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)133 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
134 uint64_t Address,
135 const void *Decoder) {
136 return decodeRegisterClass(Inst, RegNo, VSFRegs);
137 }
138
DecodeVSSRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)139 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
140 uint64_t Address,
141 const void *Decoder) {
142 return decodeRegisterClass(Inst, RegNo, VSSRegs);
143 }
144
DecodeGPRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)145 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
146 uint64_t Address,
147 const void *Decoder) {
148 return decodeRegisterClass(Inst, RegNo, RRegs);
149 }
150
DecodeGPRC_NOR0RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)151 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
152 uint64_t Address,
153 const void *Decoder) {
154 return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
155 }
156
DecodeG8RCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)157 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
158 uint64_t Address,
159 const void *Decoder) {
160 return decodeRegisterClass(Inst, RegNo, XRegs);
161 }
162
DecodeG8RC_NOX0RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)163 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
164 uint64_t Address,
165 const void *Decoder) {
166 return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
167 }
168
169 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
170 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
171
DecodeSPERCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)172 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
173 uint64_t Address,
174 const void *Decoder) {
175 return decodeRegisterClass(Inst, RegNo, SPERegs);
176 }
177
DecodeACCRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)178 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
179 uint64_t Address,
180 const void *Decoder) {
181 return decodeRegisterClass(Inst, RegNo, ACCRegs);
182 }
183
DecodeVSRpRCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)184 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
185 uint64_t Address,
186 const void *Decoder) {
187 return decodeRegisterClass(Inst, RegNo, VSRpRegs);
188 }
189
190 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
191 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
192
193 template<unsigned N>
decodeUImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)194 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
195 int64_t Address, const void *Decoder) {
196 assert(isUInt<N>(Imm) && "Invalid immediate");
197 Inst.addOperand(MCOperand::createImm(Imm));
198 return MCDisassembler::Success;
199 }
200
201 template<unsigned N>
decodeSImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)202 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
203 int64_t Address, const void *Decoder) {
204 assert(isUInt<N>(Imm) && "Invalid immediate");
205 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
206 return MCDisassembler::Success;
207 }
208
decodeImmZeroOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)209 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
210 int64_t Address, const void *Decoder) {
211 if (Imm != 0)
212 return MCDisassembler::Fail;
213 Inst.addOperand(MCOperand::createImm(Imm));
214 return MCDisassembler::Success;
215 }
216
decodeVSRpEvenOperands(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder)217 static DecodeStatus decodeVSRpEvenOperands(MCInst &Inst, uint64_t RegNo,
218 uint64_t Address,
219 const void *Decoder) {
220 if (RegNo & 1)
221 return MCDisassembler::Fail;
222 Inst.addOperand(MCOperand::createReg(VSRpRegs[RegNo >> 1]));
223 return MCDisassembler::Success;
224 }
225
decodeMemRIOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)226 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
227 int64_t Address, const void *Decoder) {
228 // Decode the memri field (imm, reg), which has the low 16-bits as the
229 // displacement and the next 5 bits as the register #.
230
231 uint64_t Base = Imm >> 16;
232 uint64_t Disp = Imm & 0xFFFF;
233
234 assert(Base < 32 && "Invalid base register");
235
236 switch (Inst.getOpcode()) {
237 default: break;
238 case PPC::LBZU:
239 case PPC::LHAU:
240 case PPC::LHZU:
241 case PPC::LWZU:
242 case PPC::LFSU:
243 case PPC::LFDU:
244 // Add the tied output operand.
245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
246 break;
247 case PPC::STBU:
248 case PPC::STHU:
249 case PPC::STWU:
250 case PPC::STFSU:
251 case PPC::STFDU:
252 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
253 break;
254 }
255
256 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
257 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
258 return MCDisassembler::Success;
259 }
260
decodeMemRIXOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)261 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
262 int64_t Address, const void *Decoder) {
263 // Decode the memrix field (imm, reg), which has the low 14-bits as the
264 // displacement and the next 5 bits as the register #.
265
266 uint64_t Base = Imm >> 14;
267 uint64_t Disp = Imm & 0x3FFF;
268
269 assert(Base < 32 && "Invalid base register");
270
271 if (Inst.getOpcode() == PPC::LDU)
272 // Add the tied output operand.
273 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
274 else if (Inst.getOpcode() == PPC::STDU)
275 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
276
277 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
278 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
279 return MCDisassembler::Success;
280 }
281
decodeMemRIHashOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)282 static DecodeStatus decodeMemRIHashOperands(MCInst &Inst, uint64_t Imm,
283 int64_t Address,
284 const void *Decoder) {
285 // Decode the memrix field for a hash store or hash check operation.
286 // The field is composed of a register and an immediate value that is 6 bits
287 // and covers the range -8 to -512. The immediate is always negative and 2s
288 // complement which is why we sign extend a 7 bit value.
289 const uint64_t Base = Imm >> 6;
290 const int64_t Disp = SignExtend64<7>((Imm & 0x3F) + 64) * 8;
291
292 assert(Base < 32 && "Invalid base register");
293
294 Inst.addOperand(MCOperand::createImm(Disp));
295 Inst.addOperand(MCOperand::createReg(RRegs[Base]));
296 return MCDisassembler::Success;
297 }
298
decodeMemRIX16Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)299 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
300 int64_t Address, const void *Decoder) {
301 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
302 // displacement with 16-byte aligned, and the next 5 bits as the register #.
303
304 uint64_t Base = Imm >> 12;
305 uint64_t Disp = Imm & 0xFFF;
306
307 assert(Base < 32 && "Invalid base register");
308
309 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
310 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
311 return MCDisassembler::Success;
312 }
313
decodeMemRI34PCRelOperands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)314 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
315 int64_t Address,
316 const void *Decoder) {
317 // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
318 // displacement, and the next 5 bits as an immediate 0.
319 uint64_t Base = Imm >> 34;
320 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
321
322 assert(Base < 32 && "Invalid base register");
323
324 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
325 return decodeImmZeroOperand(Inst, Base, Address, Decoder);
326 }
327
decodeMemRI34Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)328 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
329 int64_t Address,
330 const void *Decoder) {
331 // Decode the memri34 field (imm, reg), which has the low 34-bits as the
332 // displacement, and the next 5 bits as the register #.
333 uint64_t Base = Imm >> 34;
334 uint64_t Disp = Imm & 0x3FFFFFFFFUL;
335
336 assert(Base < 32 && "Invalid base register");
337
338 Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
339 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
340 return MCDisassembler::Success;
341 }
342
decodeSPE8Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)343 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
344 int64_t Address, const void *Decoder) {
345 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
346 // displacement with 8-byte aligned, and the next 5 bits as the register #.
347
348 uint64_t Base = Imm >> 5;
349 uint64_t Disp = Imm & 0x1F;
350
351 assert(Base < 32 && "Invalid base register");
352
353 Inst.addOperand(MCOperand::createImm(Disp << 3));
354 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
355 return MCDisassembler::Success;
356 }
357
decodeSPE4Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)358 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
359 int64_t Address, const void *Decoder) {
360 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
361 // displacement with 4-byte aligned, and the next 5 bits as the register #.
362
363 uint64_t Base = Imm >> 5;
364 uint64_t Disp = Imm & 0x1F;
365
366 assert(Base < 32 && "Invalid base register");
367
368 Inst.addOperand(MCOperand::createImm(Disp << 2));
369 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
370 return MCDisassembler::Success;
371 }
372
decodeSPE2Operands(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)373 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
374 int64_t Address, const void *Decoder) {
375 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
376 // displacement with 2-byte aligned, and the next 5 bits as the register #.
377
378 uint64_t Base = Imm >> 5;
379 uint64_t Disp = Imm & 0x1F;
380
381 assert(Base < 32 && "Invalid base register");
382
383 Inst.addOperand(MCOperand::createImm(Disp << 1));
384 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
385 return MCDisassembler::Success;
386 }
387
decodeCRBitMOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder)388 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
389 int64_t Address, const void *Decoder) {
390 // The cr bit encoding is 0x80 >> cr_reg_num.
391
392 unsigned Zeros = countTrailingZeros(Imm);
393 assert(Zeros < 8 && "Invalid CR bit value");
394
395 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
396 return MCDisassembler::Success;
397 }
398
399 #include "PPCGenDisassemblerTables.inc"
400
getInstruction(MCInst & MI,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CS) const401 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
402 ArrayRef<uint8_t> Bytes,
403 uint64_t Address,
404 raw_ostream &CS) const {
405 auto *ReadFunc = IsLittleEndian ? support::endian::read32le
406 : support::endian::read32be;
407
408 // If this is an 8-byte prefixed instruction, handle it here.
409 // Note: prefixed instructions aren't technically 8-byte entities - the prefix
410 // appears in memory at an address 4 bytes prior to that of the base
411 // instruction regardless of endianness. So we read the two pieces and
412 // rebuild the 8-byte instruction.
413 // TODO: In this function we call decodeInstruction several times with
414 // different decoder tables. It may be possible to only call once by
415 // looking at the top 6 bits of the instruction.
416 if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
417 uint32_t Prefix = ReadFunc(Bytes.data());
418 uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
419 uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
420 DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
421 this, STI);
422 if (result != MCDisassembler::Fail) {
423 Size = 8;
424 return result;
425 }
426 }
427
428 // Get the four bytes of the instruction.
429 Size = 4;
430 if (Bytes.size() < 4) {
431 Size = 0;
432 return MCDisassembler::Fail;
433 }
434
435 // Read the instruction in the proper endianness.
436 uint64_t Inst = ReadFunc(Bytes.data());
437
438 if (STI.getFeatureBits()[PPC::FeatureSPE]) {
439 DecodeStatus result =
440 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
441 if (result != MCDisassembler::Fail)
442 return result;
443 }
444
445 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
446 }
447