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Searched refs:DRC (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCondMov.td18 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
26 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
[all …]
H A DMipsInstrFPU.td216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
H A DMipsInstrInfo.td1804 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1805 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1806 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1823 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1824 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1825 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
778 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
781 switch (DRC->getID()) { in buildMux()
802 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
H A DHexagonBitSimplify.cpp933 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
934 if (!DRC) in isTransparentCopy()
937 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1484 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1485 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1492 BT.put(ImmReg, DRC); in processBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td1292 class AtomicLoad<PatFrag Op, RegisterClass DRC,
1294 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1295 [(set DRC:$rd, (Op i16:$rr))]>;
1297 class AtomicStore<PatFrag Op, RegisterClass DRC,
1299 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1300 [(Op i16:$rd, DRC:$rr)]>;
1302 class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
1304 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
1306 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineVerifier.cpp1898 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
1900 if (!DRC->contains(Reg)) { in visitMachineOperand()
1903 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2007 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2016 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2017 if (!DRC) { in visitMachineOperand()
2022 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2024 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
H A DMachineSink.cpp279 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY() local
280 if (SRC != DRC) in INITIALIZE_PASS_DEPENDENCY()
/netbsd-src/external/bsd/file/dist/magic/magdir/
H A Dringdove41 >0 regex begin\ drc\ v with PCB DRC script
/netbsd-src/sys/arch/macppc/dev/
H A Dsnapper.c625 u_char DRC[6]; member
1872 sizeof tas3004_initdata.DRC, /* 0x02 */
2113 DEQ_WRITE(sc, DEQ_DRC, tas3004_initdata.DRC); in tas3004_init()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp4598 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
4600 return DRC->contains(Reg); in isLegalRegOperand()
4610 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
4611 if (!DRC) in isLegalRegOperand()
4614 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()