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Searched refs:DPLL (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dvo.c489 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
490 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
497 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
H A Dintel_display.c1115 val = I915_READ(DPLL(pipe)); in assert_pll()
1404 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _vlv_enable_pll()
1405 POSTING_READ(DPLL(pipe)); in _vlv_enable_pll()
1408 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1454 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in _chv_enable_pll()
1457 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1491 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
1510 i915_reg_t reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1565 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1566 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
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H A Dintel_display_power.c1274 u32 val = I915_READ(DPLL(pipe)); in vlv_display_power_well_init()
1280 I915_WRITE(DPLL(pipe), val); in vlv_display_power_well_init()
1438 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
5088 u32 status = I915_READ(DPLL(PIPE_A)); in chv_phy_control_init()
H A Dintel_dp.c791 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
/netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h17 #define DPLL 3 macro
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dexynos5422-odroid-core.dtsi97 /* derived from 600MHz DPLL */
199 /* derived from 600MHz DPLL */
235 /* derived from 600MHz DPLL */
247 /* derived from 600MHz DPLL */
262 /* derived from 600MHz DPLL */
H A Drk3036.dtsi237 * Fix the emac parent clock is DPLL instead of APLL.
/netbsd-src/sys/arch/arm/samsung/
H A Dexynos_soc.c432 DUMP_PLL(5, DPLL); in exynos_dump_clocks()
/netbsd-src/sys/arch/evbarm/conf/
H A DGENERIC170 tidpllclk* at fdt? pass 2 # TI DPLL clock
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h3363 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro