Searched refs:DDR_BASE (Results 1 – 3 of 3) sorted by relevance
| /netbsd-src/sys/arch/arm/broadcom/ |
| H A D | bcm53xx_board.c | 153 const uint32_t v01 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_01); in bcm53xx_memprobe()
154 const uint32_t v82 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_82); in bcm53xx_memprobe()
155 const uint32_t v86 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_86); in bcm53xx_memprobe()
156 const uint32_t v87 = bus_space_read_4(bst, bsh, DDR_BASE + DDR_CTL_87); in bcm53xx_memprobe()
405 DDR_BASE + DDR_PHY_CTL_PLL_STATUS); in bcm53xx_get_chip_ioreg_state()
407 DDR_BASE + DDR_PHY_CTL_PLL_DIVIDERS); in bcm53xx_get_chip_ioreg_state()
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| H A D | bcm53xx_ccb.c | 115 { "bcmddr", DDR_BASE, 0x1000, BCMCCBCF_PORT_DEFAULT, 1, { IRQ_DDR_CONTROLLER } },
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| H A D | bcm53xx_reg.h | 127 #define DDR_BASE 0x010000 macro
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