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Searched refs:Cycles (Results 1 – 25 of 49) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp44 unsigned int Cycles; member
46 VisitedBBInfo() : HasReturn(false), Cycles(0) {} in VisitedBBInfo()
47 VisitedBBInfo(bool HasReturn, unsigned int Cycles) in VisitedBBInfo()
48 : HasReturn(HasReturn), Cycles(Cycles) {} in VisitedBBInfo()
76 unsigned int Cycles = 0);
79 unsigned int &Cycles);
135 unsigned Cycles = I->second; in runOnMachineFunction() local
142 if (Cycles < Threshold) { in runOnMachineFunction()
154 addPadding(MBB, ReturnLoc, Threshold - Cycles); in runOnMachineFunction()
165 void PadShortFunc::findReturns(MachineBasicBlock *MBB, unsigned int Cycles) { in findReturns() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/
H A DInstruction.cpp22 unsigned Cycles) { in writeStartEvent() argument
25 CRD.Cycles = Cycles; in writeStartEvent()
26 DependentWriteCyclesLeft = Cycles; in writeStartEvent()
31 unsigned Cycles) { in writeStartEvent() argument
41 if (TotalCycles < Cycles) { in writeStartEvent()
44 CRD.Cycles = Cycles; in writeStartEvent()
45 TotalCycles = Cycles; in writeStartEvent()
132 if (CriticalRegDep.Cycles) in computeCriticalRegDep()
138 if (WriteCRD.Cycles > MaxLatency) in computeCriticalRegDep()
144 if (ReadCRD.Cycles > MaxLatency) in computeCriticalRegDep()
H A DPipeline.cpp45 ++Cycles; in run()
48 return Cycles; in run()
86 LLVM_DEBUG(dbgs() << "\n[E] Cycle begin: " << Cycles << '\n'); in notifyCycleBegin()
92 LLVM_DEBUG(dbgs() << "[E] Cycle end: " << Cycles << "\n"); in notifyCycleEnd()
H A DInstrBuilder.cpp68 if (!PRE->Cycles) { in initializeUsedResources()
88 CycleSegment RCy(0, PRE->Cycles, false); in initializeUsedResources()
92 SuperResources[Super] += PRE->Cycles; in initializeUsedResources()
331 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
359 WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles); in populateWrites()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCSchedule.h66 uint16_t Cycles; member
69 return ProcResourceIdx == Other.ProcResourceIdx && Cycles == Other.Cycles;
79 int16_t Cycles; member
83 return Cycles == Other.Cycles && WriteResourceID == Other.WriteResourceID;
98 int Cycles; member
102 && Cycles == Other.Cycles;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/
H A DMCSchedule.cpp49 if (WLEntry->Cycles < 0) in computeInstrLatency()
50 return WLEntry->Cycles; in computeInstrLatency()
51 Latency = std::max(Latency, static_cast<int>(WLEntry->Cycles)); in computeInstrLatency()
95 if (!I->Cycles) in getReciprocalThroughput()
98 double Temp = NumUnits * 1.0 / I->Cycles; in getReciprocalThroughput()
163 DelayCycles = std::min(DelayCycles, E.Cycles); in getForwardingDelayCycles()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/Views/
H A DTimelineView.cpp22 unsigned Cycles) in TimelineView() argument
24 MaxCycle(Cycles == 0 ? 80 : Cycles), LastCycle(0), WaitTime(S.size()), in TimelineView()
121 static void tryChangeColor(raw_ostream &OS, unsigned Cycles, in tryChangeColor() argument
126 raw_ostream::Colors Color = chooseColor(Cycles, Executions, BufferSize); in tryChangeColor()
256 static void printTimelineHeader(formatted_raw_ostream &OS, unsigned Cycles) { in printTimelineHeader() argument
258 if (Cycles >= 10) { in printTimelineHeader()
260 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
271 for (unsigned I = 0; I <= Cycles; ++I) { in printTimelineHeader()
H A DBottleneckAnalysis.cpp507 unsigned Cycles = 2 * Tracker.getResourcePressureCycles(IID); in onEvent() local
514 addResourceDep(U.first % Source.size(), To, Current, U.second + Cycles); in onEvent()
520 if (RegDep.Cycles) { in onEvent()
521 Cycles = RegDep.Cycles + 2 * Tracker.getRegisterPressureCycles(IID); in onEvent()
523 addRegisterDep(From, To, RegDep.RegID, Cycles); in onEvent()
527 if (MemDep.Cycles) { in onEvent()
528 Cycles = MemDep.Cycles + 2 * Tracker.getMemoryPressureCycles(IID); in onEvent()
530 addMemoryDep(From, To, Cycles); in onEvent()
H A DTimelineView.h167 unsigned Cycles);
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/HardwareUnits/
H A DLSUnit.h122 unsigned Cycles = IR.getInstruction()->getCyclesLeft(); in onGroupIssued() local
123 if (CriticalPredecessor.Cycles < Cycles) { in onGroupIssued()
125 CriticalPredecessor.Cycles = Cycles; in onGroupIssued()
187 if (isWaiting() && CriticalPredecessor.Cycles) in cycleEvent()
188 CriticalPredecessor.Cycles--; in cycleEvent()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DEarlyIfConversion.cpp855 struct Cycles { struct
859 template <typename Remark> Remark &operator<<(Remark &R, Cycles C) { in operator <<()
902 << Cycles{"ResLength", ResLength} in shouldConvertIf()
904 << Cycles{"MinCrit", MinCrit} << ") by more than the threshold of " in shouldConvertIf()
905 << Cycles{"CritLimit", CritLimit} in shouldConvertIf()
988 << Cycles{"CondCycles", Cond.Extra} << " to the critical path"; in shouldConvertIf()
991 << Cycles{"ShortCycles", Short.Extra}; in shouldConvertIf()
994 << Cycles{"LongCycles", Long.Extra}; in shouldConvertIf()
996 << Cycles{"CritLimit", CritLimit} << "."; in shouldConvertIf()
1004 << Cycles{"CondCycles", Cond.Extra} << " to the critical path"; in shouldConvertIf()
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H A DTargetSchedule.cpp126 static unsigned capLatency(int Cycles) { in capLatency() argument
127 return Cycles >= 0 ? Cycles : 1000; in capLatency()
224 unsigned Latency = capLatency(WLEntry->Cycles); in computeOperandLatency()
H A DMachineTraceMetrics.cpp130 PRCycles[PI->ProcResourceIdx] += PI->Cycles; in getResources()
583 Cycles.erase(&I); in invalidate()
775 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
800 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
808 InstrCycles &MICycles = Cycles[&UseMI]; in updateDepth()
1082 unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0; in computeInstrHeights()
1121 InstrCycles &MICycles = Cycles[&MI]; in computeInstrHeights()
1237 unsigned Cycles = 0; in getResourceLength() local
1247 Cycles += in getResourceLength()
1248 (PI->Cycles * TE.MTM.SchedModel.getResourceFactor(ResourceIdx)); in getResourceLength()
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H A DMachineScheduler.cpp2034 RemainingCounts[PIdx] += (Factor * PI->Cycles); in init()
2087 unsigned Cycles) { in getNextResourceCycleByInstance() argument
2094 NextUnreserved += Cycles; in getNextResourceCycleByInstance()
2103 unsigned Cycles) { in getNextResourceCycle() argument
2132 getNextResourceCycle(SC, SubUnits[I], Cycles); in getNextResourceCycle()
2143 unsigned NextUnreserved = getNextResourceCycleByInstance(I, Cycles); in getNextResourceCycle()
2192 unsigned Cycles = PE.Cycles; in checkHazard() local
2194 std::tie(NRCycle, InstanceIdx) = getNextResourceCycle(SC, ResIdx, Cycles); in checkHazard()
2197 MaxObservedStall = std::max(Cycles, MaxObservedStall); in checkHazard()
2345 unsigned Cycles, unsigned NextCycle) { in countResource() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
H A DInstruction.h90 unsigned Cycles; member
204 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
276 void writeStartEvent(unsigned IID, MCPhysReg RegID, unsigned Cycles);
320 void subtract(unsigned Cycles) { in subtract() argument
321 assert(End >= Cycles); in subtract()
322 End -= Cycles; in subtract()
340 ResourceUsage(CycleSegment Cycles, unsigned Units = 1)
341 : CS(Cycles), NumUnits(Units) {} in CS()
H A DPipeline.h57 unsigned Cycles; variable
65 Pipeline() : Cycles(0) {} in Pipeline()
H A DSupport.h55 ResourceCycles(unsigned Cycles, unsigned ResourceUnits = 1)
56 : Numerator(Cycles), Denominator(ResourceUnits) {} in Numerator() argument
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/
H A DSchedClassResolution.cpp66 Result.push_back({WPR->ProcResourceIdx, WPR->Cycles}); in getNonRedundantWriteProcRes()
67 ProcResUnitUsage[WPR->ProcResourceIdx] += WPR->Cycles; in getNonRedundantWriteProcRes()
71 float RemainingCycles = WPR->Cycles; in getNonRedundantWriteProcRes()
188 DensePressure[WPR.ProcResourceIdx] += WPR.Cycles; in computeIdealizedProcResPressure()
194 distributePressure(WPR.Cycles, Subunits, DensePressure); in computeIdealizedProcResPressure()
278 std::max<double>(LatencyMeasure.PerInstructionValue, WLE->Cycles); in getAsPoint()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp111 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
308 int Cycles = Stage->getValueAsInt("Cycles"); in FormItineraryStageString() local
309 ItinString += " { " + itostr(Cycles) + ", "; in FormItineraryStageString()
933 std::vector<int64_t> &Cycles, in ExpandProcResources() argument
935 assert(PRVec.size() == Cycles.size() && "failed precondition"); in ExpandProcResources()
955 Cycles.push_back(Cycles[i]); in ExpandProcResources()
971 Cycles.push_back(Cycles[i]); in ExpandProcResources()
1072 WLEntry.Cycles = 0; in GenSchedClassTables()
1093 WLEntry.Cycles += WriteRes->getValueAsInt("Latency"); in GenSchedClassTables()
1103 std::vector<int64_t> Cycles = in GenSchedClassTables() local
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/MCA/Stages/
H A DInstructionTables.cpp32 unsigned Cycles = Resource.second.size(); in execute() local
41 std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits))); in execute()
56 ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits))); in execute()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZHazardRecognizer.cpp190 if (PI->Cycles > 1) in dumpSU()
191 OS << "(" << PI->Cycles << "cyc)"; in dumpSU()
304 CurrCounter += PI->Cycles; in EmitInstruction()
404 Cost = PI->Cycles; in resourcesCost()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineTraceMetrics.h299 return TE.Cycles.lookup(&MI); in getInstrCycles()
325 DenseMap<const MachineInstr*, InstrCycles> Cycles; variable
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetItinerary.td43 // the execution of an instruction. Cycles represents the number of
52 // InstrStage<1, [FU_x, FU_y]> - TimeInc defaults to Cycles
59 int Cycles = cycles; // length of stage in machine cycles
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp383 unsigned Cycles[3] = { 2, 1, 0}; in getTransSwizzle() local
384 return Cycles[Op]; in getTransSwizzle()
387 unsigned Cycles[3] = { 1, 2, 2}; in getTransSwizzle() local
388 return Cycles[Op]; in getTransSwizzle()
391 unsigned Cycles[3] = { 2, 1, 2}; in getTransSwizzle() local
392 return Cycles[Op]; in getTransSwizzle()
395 unsigned Cycles[3] = { 2, 2, 1}; in getTransSwizzle() local
396 return Cycles[Op]; in getTransSwizzle()
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp291 Expected<unsigned> Cycles = P.run(); in runPipeline() local
292 if (!Cycles) { in runPipeline()
293 WithColor::error() << toString(Cycles.takeError()); in runPipeline()

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