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Searched refs:CondReg (Results 1 – 20 of 20) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
773 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
774 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg()
776 if (CondReg) in getCondOrInverseInReg()
777 return {CondReg, false}; in getCondOrInverseInReg()
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic() local
828 if (!CondReg) in rewriteArithmetic()
829 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in rewriteArithmetic()
838 .addReg(CondReg) in rewriteArithmetic()
854 unsigned CondReg; in rewriteCMov() local
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H A DX86FastISel.cpp2120 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2121 if (CondReg == 0) in X86FastEmitCMoveSelect()
2125 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2126 unsigned KCondReg = CondReg; in X86FastEmitCMoveSelect()
2127 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2129 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2131 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2134 .addReg(CondReg) in X86FastEmitCMoveSelect()
2318 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2319 if (CondReg == 0) in X86FastEmitPseudoSelect()
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H A DX86InstructionSelector.cpp1363 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1368 .addReg(CondReg) in selectCondBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp81 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
96 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
97 if (!A->definesRegister(CondReg, TRI) || in optimizeVccBranch()
102 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
153 if (!MI.killsRegister(CondReg, TRI)) { in optimizeVccBranch()
156 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
159 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
216 MI.RemoveOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI)); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp39 MCRegister CondReg; member in __anonb4c9c4b40111::SIOptimizeExecMaskingPreRA
133 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
207 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
210 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
320 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in runOnMachineFunction()
H A DAMDGPURegisterBankInfo.cpp817 Register CondReg; in executeInWaterfallLoop() local
866 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
868 CondReg = NewCondReg; in executeInWaterfallLoop()
884 .addReg(CondReg); in executeInWaterfallLoop()
885 CondReg = AndReg; in executeInWaterfallLoop()
961 bool First = CondReg == AMDGPU::NoRegister; in executeInWaterfallLoop()
963 CondReg = NewCondReg; in executeInWaterfallLoop()
977 .addReg(CondReg); in executeInWaterfallLoop()
978 CondReg = AndReg; in executeInWaterfallLoop()
1005 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
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H A DSIInstrInfo.cpp2412 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
2414 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
2415 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
2468 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
2469 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
2470 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
5147 Register CondReg = AMDGPU::NoRegister; in emitLoadSRsrcFromVGPRLoop() local
5190 if (CondReg == AMDGPU::NoRegister) // First. in emitLoadSRsrcFromVGPRLoop()
5191 CondReg = NewCondReg; in emitLoadSRsrcFromVGPRLoop()
5195 .addReg(CondReg) in emitLoadSRsrcFromVGPRLoop()
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H A DAMDGPUInstructionSelector.cpp2430 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
2442 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
2443 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
2460 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
2461 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
2464 .addReg(CondReg); in selectG_BRCOND()
H A DVOP3Instructions.td739 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
743 (i1 CondReg)),
H A DAMDGPUMachineCFGStructurizer.cpp1874 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
1875 for (auto UI = MRI->use_begin(CondReg), E = MRI->use_end(); UI != E; ++UI) { in ensureCondIsNotKilled()
H A DAMDGPUISelDAGToDAG.cpp2275 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2302 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
H A DSIISelLowering.cpp3509 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
3528 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
3536 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
3538 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp912 unsigned CondReg = getRegForI1Value(Select->getCondition(), Not); in selectSelect() local
913 if (CondReg == 0) in selectSelect()
965 .addReg(CondReg); in selectSelect()
1312 unsigned CondReg = getRegForI1Value(Br->getCondition(), Not); in selectBr() local
1313 if (CondReg == 0) in selectBr()
1322 .addReg(CondReg); in selectBr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp967 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
968 if (CondReg == 0) in selectBranch()
971 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1046 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
1048 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1055 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp774 auto CondReg = MIB.getReg(1); in selectSelect() local
775 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
778 .addUse(CondReg) in selectSelect()
H A DARMFastISel.cpp1607 unsigned CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1608 if (CondReg == 0) return false; in SelectSelect()
1634 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1637 .addReg(CondReg) in SelectSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2457 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2458 if (!CondReg) in selectBranch()
2471 unsigned CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2472 if (CondReg == 0) in selectBranch()
2484 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2693 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2694 if (!CondReg) in selectSelect()
2742 unsigned CondReg = getRegForValue(Cond); in selectSelect() local
2743 if (!CondReg) in selectSelect()
2747 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1583 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1584 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1586 CondReg = CCMI->getOperand(1).getReg(); in selectCompareBranch()
1587 CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1602 emitTestBit(CondReg, /*Bit = */ 0, /*IsNegative = */ true, in selectCompareBranch()
1610 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
3093 const Register CondReg = I.getOperand(1).getReg(); in select() local
3103 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp786 unsigned CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
789 CondReg, PPCPred)) in SelectBranch()
794 .addReg(CondReg) in SelectBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp3515 Register CondReg = MI.getOperand(1).getReg(); in fewerElementsVectorSelect() local
3521 LLT CondTy = MRI.getType(CondReg); in fewerElementsVectorSelect()
3569 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, in fewerElementsVectorSelect()
5089 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
5090 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
5112 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
5118 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()