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/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
H A DSimpleConstraintManager.cpp26 DefinedSVal Cond, in assume() argument
29 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
38 Cond = SVB.evalCast(*LV, SVB.getContext().BoolTy, T).castAs<DefinedSVal>(); in assume()
41 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assume()
45 NonLoc Cond, bool Assumption) { in assume() argument
46 State = assumeAux(State, Cond, Assumption); in assume()
48 return EE->processAssume(State, Cond, Assumption); in assume()
53 NonLoc Cond, in assumeAux() argument
58 if (!canReasonAbout(Cond)) { in assumeAux()
60 SymbolRef Sym = Cond.getAsSymbol(); in assumeAux()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp107 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
125 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
126 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
133 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
134 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
176 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const { in insertBranch() argument
179 if (Cond.empty()) { in insertBranch()
187 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
189 if (Cond[0].getImm()) in insertBranch()
190 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
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H A DWebAssemblyLowerBrUnless.cpp71 Register Cond = MI->getOperand(1).getReg(); in runOnMachineFunction() local
75 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
76 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
77 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
178 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
193 .addReg(Cond); in runOnMachineFunction()
195 Cond = Tmp; in runOnMachineFunction()
204 .addReg(Cond); in runOnMachineFunction()
H A DWebAssemblyFixBrTableDefaults.cpp97 SmallVector<MachineOperand, 2> Cond; in fixBrTableDefault() local
99 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond); in fixBrTableDefault()
114 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info"); in fixBrTableDefault()
123 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
H A DLibCallsShrinkWrap.cpp95 void shrinkWrapCI(CallInst *CI, Value *Cond);
138 Value *Cond = nullptr; in performCallDomainErrorOnly() local
149 Cond = createOrCond(CI, CmpInst::FCMP_OLT, -1.0f, CmpInst::FCMP_OGT, 1.0f); in performCallDomainErrorOnly()
160 Cond = createOrCond(CI, CmpInst::FCMP_OEQ, INFINITY, CmpInst::FCMP_OEQ, in performCallDomainErrorOnly()
169 Cond = createCond(CI, CmpInst::FCMP_OLT, 1.0f); in performCallDomainErrorOnly()
177 Cond = createCond(CI, CmpInst::FCMP_OLT, 0.0f); in performCallDomainErrorOnly()
183 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
190 Value *Cond = nullptr; in performCallRangeErrorOnly() local
208 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
215 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
133 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
135 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
159 Cond[0].setImm(CC); in reverseBranchCondition()
166 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
201 Cond.clear(); in analyzeBranch()
225 if (Cond.empty()) { in analyzeBranch()
228 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
234 assert(Cond.size() == 1); in analyzeBranch()
242 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm(); in analyzeBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp192 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
274 ArrayRef<MachineOperand> Cond, in insertBranch() argument
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
289 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp173 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
351 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
352 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
353 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
373 ArrayRef<MachineOperand> Cond, in insertBranch() argument
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp1376 unsigned Cond = 0; in LowerXALUO() local
1383 Cond = M68k::COND_VS; in LowerXALUO()
1387 Cond = M68k::COND_CS; in LowerXALUO()
1391 Cond = M68k::COND_VS; in LowerXALUO()
1395 Cond = M68k::COND_CS; in LowerXALUO()
1403 DAG.getConstant(Cond, DL, MVT::i8), in LowerXALUO()
1427 M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ; in getBitTestCondition() local
1429 DAG.getConstant(Cond, DL, MVT::i8), BT); in getBitTestCondition()
1971 SDValue Cond = Op.getOperand(3); in LowerSETCCCARRY() local
1975 M68k::CondCode CC = TranslateIntegerM68kCC(cast<CondCodeSDNode>(Cond)->get()); in LowerSETCCCARRY()
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H A DM68kInstrInfo.cpp85 SmallVectorImpl<MachineOperand> &Cond, in AnalyzeBranchImpl() argument
133 Cond.clear(); in AnalyzeBranchImpl()
160 if (Cond.empty()) { in AnalyzeBranchImpl()
207 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranchImpl()
213 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranchImpl()
222 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in AnalyzeBranchImpl()
230 assert(Cond.size() == 1); in AnalyzeBranchImpl()
234 auto OldBranchCode = static_cast<M68k::CondCode>(Cond[0].getImm()); in AnalyzeBranchImpl()
251 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
253 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, AllowModify); in analyzeBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.cpp98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
116 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
134 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
183 ArrayRef<MachineOperand> Cond, in insertBranch() argument
190 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
195 if (Cond.empty()) // Unconditional branch in insertBranch()
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in insertBranch()
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in insertBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFAdjustOpt.cpp182 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
183 if (!Cond || B2->getFirstNonPHI() != Cond) in serializeICMPCrossBB()
185 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
186 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
192 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
193 if (!Cond) in serializeICMPCrossBB()
195 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
196 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
211 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp82 SmallVectorImpl<MachineOperand> &Cond) const { in AnalyzeCondBr()
89 Cond.push_back(MachineOperand::CreateImm(Opc)); in AnalyzeCondBr()
92 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
101 BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); in analyzeBranch()
108 ArrayRef<MachineOperand> Cond) const { in BuildCondBr()
109 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
113 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
114 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
116 MIB.add(Cond[i]); in BuildCondBr()
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H A DMipsInstrInfo.h65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
185 SmallVectorImpl<MachineOperand> &Cond) const;
188 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp102 const DebugLoc &TestLoc, X86::CondCode Cond);
105 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs);
740 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
741 if (Cond != X86::COND_INVALID && !MI.mayStore() && in collectCondsInRegs()
745 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
758 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
761 TII->get(X86::SETCCr), Reg).addImm(Cond); in promoteCondToReg()
770 const DebugLoc &TestLoc, X86::CondCode Cond, CondRegArray &CondRegs) { in getCondOrInverseInReg() argument
771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
772 unsigned &InvCondReg = CondRegs[X86::GetOppositeBranchCondition(Cond)]; in getCondOrInverseInReg()
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H A DX86InstrCMovSetCC.td87 multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
88 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
90 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
92 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
94 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
96 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
98 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
101 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
102 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp266 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
306 Cond.clear(); in analyzeBranch()
330 if (Cond.empty()) { in analyzeBranch()
371 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
377 assert(Cond.size() == 1); in analyzeBranch()
386 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm(); in analyzeBranch()
401 ArrayRef<MachineOperand> Cond, in insertBranch() argument
408 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
411 if (Cond.empty()) { in insertBranch()
421 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp138 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
139 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(0).getImm())); in parseCondBranch()
140 Cond.push_back(LastInst->getOperand(1)); in parseCondBranch()
141 Cond.push_back(LastInst->getOperand(2)); in parseCondBranch()
147 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
168 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
201 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
229 ArrayRef<MachineOperand> Cond, in insertBranch() argument
232 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
235 if (Cond.empty()) { in insertBranch()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DGuardUtils.cpp66 auto *Cond = BI->getCondition(); in parseWidenableBranch() local
67 if (!Cond->hasOneUse()) in parseWidenableBranch()
73 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
85 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp394 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
398 Cond.clear(); in analyzeBranch()
489 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
490 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
495 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
496 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
502 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode())); in analyzeBranch()
503 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
504 Cond.push_back(LastInst->getOperand(1)); in analyzeBranch()
519 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode())); in analyzeBranch()
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/netbsd-src/external/apache2/llvm/dist/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DConstraintManager.h86 DefinedSVal Cond,
93 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
94 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
100 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
105 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp154 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
155 Cond.push_back(MachineOperand::CreateImm(LastInst->getOperand(1).getImm())); in parseCondBranch()
162 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
183 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
217 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
245 ArrayRef<MachineOperand> Cond, in insertBranch() argument
249 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
253 if (Cond.empty()) { in insertBranch()
260 unsigned CC = Cond[0].getImm(); in insertBranch()
298 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIAnnotateControlFlow.cpp83 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
224 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
225 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
234 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
239 if (isa<Constant>(Cond)) { in handleLoopCondition()
240 Instruction *Insert = Cond == BoolTrue ? in handleLoopCondition()
243 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
263 Value *Cond = Term->getCondition(); in handleLoop() local
265 Value *Arg = handleLoopCondition(Cond, Broken, L, Term); in handleLoop()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DLoopUnswitch.cpp262 void unswitchTrivialCondition(Loop *L, Value *Cond, Constant *Val,
435 static Value *findLIVLoopCondition(Value *Cond, Loop *L, bool &Changed, in findLIVLoopCondition() argument
439 auto CacheIt = Cache.find(Cond); in findLIVLoopCondition()
447 if (Cond->getType()->isVectorTy()) in findLIVLoopCondition()
451 if (isa<Constant>(Cond)) return nullptr; in findLIVLoopCondition()
456 if (L->makeLoopInvariant(Cond, Changed, nullptr, MSSAU)) { in findLIVLoopCondition()
457 Cache[Cond] = Cond; in findLIVLoopCondition()
458 return Cond; in findLIVLoopCondition()
462 if (BinaryOperator *BO = dyn_cast<BinaryOperator>(Cond)) in findLIVLoopCondition()
497 Cache[Cond] = LHS; in findLIVLoopCondition()
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/netbsd-src/external/apache2/llvm/dist/clang/lib/Sema/
H A DScopeInfo.cpp166 if (const ConditionalOperator *Cond = dyn_cast<ConditionalOperator>(E)) { in markSafeWeakUse() local
167 markSafeWeakUse(Cond->getTrueExpr()); in markSafeWeakUse()
168 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()
172 if (const BinaryConditionalOperator *Cond = in markSafeWeakUse() local
174 markSafeWeakUse(Cond->getCommon()); in markSafeWeakUse()
175 markSafeWeakUse(Cond->getFalseExpr()); in markSafeWeakUse()

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