| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeFloatTypes.cpp | 2534 EVT CastVT = CastVal.getValueType(); in BitcastToInt_ATOMIC_SWAP() local
2537 = DAG.getAtomic(ISD::ATOMIC_SWAP, SL, CastVT, in BitcastToInt_ATOMIC_SWAP()
2538 DAG.getVTList(CastVT, MVT::Other), in BitcastToInt_ATOMIC_SWAP()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 3366 EVT CastVT = getPromotedVTForPredicate(InVT); in LowerVectorINT_TO_FP() local
3367 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
3379 MVT CastVT = in LowerVectorINT_TO_FP() local
3382 In = DAG.getNode(Opc, dl, CastVT, In); in LowerVectorINT_TO_FP()
3388 EVT CastVT = VT.changeVectorElementTypeToInteger(); in LowerVectorINT_TO_FP() local
3389 In = DAG.getNode(CastOpc, dl, CastVT, In); in LowerVectorINT_TO_FP()
8756 EVT CastVT = VT.getHalfNumVectorElementsVT(*DAG.getContext()); in tryFormConcatFromShuffle() local
8758 V0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V0, in tryFormConcatFromShuffle()
8762 V1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, CastVT, V1, in tryFormConcatFromShuffle()
8951 auto getScaledOffsetDup = [](SDValue BitCast, int &LaneC, MVT &CastVT) { in constructDup() argument
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 13815 MVT CastVT = MVT::getVectorVT(VT.getVectorElementType(), NumSrcElts); in lowerShuffleAsBroadcast() local
13816 return DAG.getNode(Opcode, DL, VT, DAG.getBitcast(CastVT, V)); in lowerShuffleAsBroadcast()
18610 MVT CastVT = MVT::getVectorVT(MVT::i8, NumElts * 2); in LowerVSELECT() local
18611 Cond = DAG.getBitcast(CastVT, Cond); in LowerVSELECT()
18612 LHS = DAG.getBitcast(CastVT, LHS); in LowerVSELECT()
18613 RHS = DAG.getBitcast(CastVT, RHS); in LowerVSELECT()
18614 SDValue Select = DAG.getNode(ISD::VSELECT, dl, CastVT, Cond, LHS, RHS); in LowerVSELECT()
23016 EVT CastVT = EVT(VT).changeVectorElementTypeToInteger(); in LowerVSETCC() local
23017 Cmp = DAG.getBitcast(CastVT, Cmp); in LowerVSETCC()
23019 DAG.getConstant(0, dl, CastVT), ISD::SETNE); in LowerVSETCC()
[all …]
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| H A D | X86InstrAVX512.td | 1789 X86VectorVTInfo CastVT> {
1793 (CastVT.VT _.RC:$src1))),
1795 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1801 (CastVT.VT _.RC:$src1))),
1803 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
1808 (IdxVT.VT (bitconvert (CastVT.VT _.RC:$src1))),
1810 (_.VT (bitconvert (CastVT.VT _.RC:$src1))))),
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 4667 EVT CastVT = getEquivalentMemType(*DAG.getContext(), LoadVT); in lowerIntrinsicLoad() local
4668 SDVTList VTList = DAG.getVTList(CastVT, MVT::Other); in lowerIntrinsicLoad()
4669 SDValue MemNode = getMemIntrinsicNode(Opc, DL, VTList, Ops, CastVT, in lowerIntrinsicLoad()
5820 static SDValue padEltsToUndef(SelectionDAG &DAG, const SDLoc &DL, EVT CastVT, in padEltsToUndef() argument
5835 return DAG.getBuildVector(CastVT, DL, Elts); in padEltsToUndef()
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