| /netbsd-src/crypto/external/bsd/openssl/dist/test/recipes/30-test_evp_data/ |
| H A D | evpciph_aes_cts.txt | 41 # Manually edited using the same inputs to also produce CS1 ciphertext
45 # 17 bytes Input((Default is CS1 if CTSMode is not specified)
55 CTSMode = CS1
64 CTSMode = CS1
79 # 64 bytes input (CS1 is equivalent to CBC when the last block in full)
81 CTSMode = CS1
93 CTSMode = CS1
101 CTSMode = CS1
109 CTSMode = CS1
117 CTSMode = CS1
[all …]
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| /netbsd-src/external/gpl3/gcc/dist/libgcc/config/libbid/ |
| H A D | bid64_sqrt.c | 216 UINT128 CX, CX2, A10, S2, T128, CS, CSM, CS2, C256, CS1, in bid64_sqrt() local
359 __sqr64_fast (CS1, CS0) in bid64_sqrt()
360 if ((CS1.w[0] != A10.w[0]) || (CS1.w[1] != A10.w[1])) { in bid64_sqrt()
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| /netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/libbid/ |
| H A D | bid64_sqrt.c | 216 UINT128 CX, CX2, A10, S2, T128, CS, CSM, CS2, C256, CS1, in bid64_sqrt() local
359 __sqr64_fast (CS1, CS0) in bid64_sqrt()
360 if ((CS1.w[0] != A10.w[0]) || (CS1.w[1] != A10.w[1])) { in bid64_sqrt()
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
| H A D | omap3430-sdp.dts | 51 <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */
104 reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
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| H A D | intel-ixp46x-ixdp465.dts | 26 /* 32 MB of Flash mapped in at CS0 and CS1 */
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| H A D | armada-370-xp.dtsi | 271 <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */
289 <MBUS_ID(0x01, 0x5a) 0 0xffffffff>, /* CS1 */
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| H A D | intel-ixp42x-netgear-wg302v2.dts | 42 * mapped in at CS0 and CS1
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| H A D | armada-388-clearfog.dts | 176 * CS1:
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| H A D | intel-ixp42x-adi-coyote.dts | 43 * mapped in at CS0 and CS1
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| H A D | imx6dl-riotboard.dts | 414 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */
428 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */
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| H A D | imx6qdl-ts4900.dtsi | 166 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */
176 MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */
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| H A D | omap3-overo-common-lcd35.dtsi | 123 reg = <1>; /* CS1 */
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| H A D | imx6dl-colibri-eval-v3.dts | 234 /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */
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| H A D | intel-ixp42x-arcom-vulcan.dts | 46 * mapped in at CS0 and CS1.
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| H A D | armada-388-clearfog.dtsi | 232 * CS1: PIC microcontroller (Pro models)
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| H A D | logicpd-som-lv-baseboard.dtsi | 65 1 0 0x2c000000 0x1000000 /* CS1: 16MB for LAN9221 */
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| H A D | intel-ixp43x-gateworks-gw2358.dts | 88 * mapped in at CS0 and CS1
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| H A D | imx6ul-kontron-n6x1x-s.dtsi | 252 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
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| H A D | omap3-ldp.dts | 98 <1 0 0x08000000 0x1000000>; /* CS1 space, 16MB */
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| H A D | imx6qdl-var-dart.dtsi | 224 /* SPI1 CS1 */
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/microchip/ |
| H A D | sparx5_pcb125.dts | 61 reg = <1>; /* CS1 */
|
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 169 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>;
188 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>;
399 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
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| H A D | HexagonRegisterInfo.cpp | 172 Reserved.set(Hexagon::CS1); // C13 in getReservedRegs()
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| /netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/ti/ |
| H A D | k3-j7200-som-p0.dtsi | 138 <0x01 0x00 0x05 0x04000000 0x800000>; /* 8MB RAM on CS1 */
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/ |
| H A D | AliasAnalysis.rst | 151 dependencies between function calls. This method takes two call sites (``CS1``
153 written by the other, ``Ref`` if ``CS1`` reads memory written by ``CS2``,
154 ``Mod`` if ``CS1`` writes to memory read or written by ``CS2``, or ``ModRef`` if
155 ``CS1`` might read or write memory written to by ``CS2``. Note that this
|