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Searched refs:CPol (Results 1 – 16 of 16) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSMInstructions.td127 (ins baseClass:$sbase, i32imm:$offset, CPol:$cpol),
138 (ins baseClass:$sbase, SReg_32:$soff, CPol:$cpol),
151 (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, CPol:$cpol),
160 (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, CPol:$cpol),
249 Operand CPolTy = !if(isRet, CPol_GLC1, CPol)> :
471 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol);
477 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
526 let InOperandList = (ins immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
529 let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, CPol:$cpol);
547 …OperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smem_offset:$offset, CPol:$cpol);
[all …]
H A DSIMemoryLegalizer.cpp278 AMDGPU::CPol::CPol Bit) const;
361 return enableNamedBit(MI, AMDGPU::CPol::GLC); in enableGLCBit()
367 return enableNamedBit(MI, AMDGPU::CPol::SLC); in enableSLCBit()
463 return enableNamedBit(MI, AMDGPU::CPol::DLC); in enableDLCBit()
764 AMDGPU::CPol::CPol Bit) const { in enableNamedBit()
765 MachineOperand *CPol = TII->getNamedOperand(*MI, AMDGPU::OpName::cpol); in enableNamedBit() local
766 if (!CPol) in enableNamedBit()
769 CPol->setImm(CPol->getImm() | Bit); in enableNamedBit()
H A DMIMGInstructions.td266 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
279 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
291 Dim:$dim, UNorm:$unorm, CPol:$cpol,
304 Dim:$dim, UNorm:$unorm, CPol:$cpol,
392 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
406 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
418 DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
432 Dim:$dim, UNorm:$unorm, CPol:$cpol,
510 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
523 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
[all …]
H A DSILoadStoreOptimizer.cpp107 unsigned CPol = 0; member
533 CPol = TII.getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
790 CI.CPol == Paired.CPol && in offsetsCanBeCombined()
791 (CI.InstClass == S_BUFFER_LOAD_IMM || CI.CPol == Paired.CPol); in offsetsCanBeCombined()
1292 .addImm(CI.CPol) // cpol in mergeSBufferLoadImmPair()
1351 .addImm(CI.CPol) // cpol in mergeBufferLoadPair()
1416 .addImm(CI.CPol) // cpol in mergeTBufferLoadPair()
1494 .addImm(CI.CPol) // cpol in mergeTBufferStorePair()
1646 .addImm(CI.CPol) // cpol in mergeBufferStorePair()
H A DSIDefines.h279 namespace CPol {
281 enum CPol { enum
H A DAMDGPUInstructionSelector.cpp1589 unsigned CPol = MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(); in selectImageIntrinsic() local
1591 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in selectImageIntrinsic()
1592 if (CPol & ~AMDGPU::CPol::ALL) in selectImageIntrinsic()
1682 MIB.addImm(CPol); in selectImageIntrinsic()
2414 MIB.addImm(AMDGPU::CPol::GLC); in selectG_AMDGPU_ATOMIC_CMPXCHG()
4243 MIB.addImm(AMDGPU::CPol::GLC); // cpol in selectMUBUFAddr64Atomic()
4268 [=](MachineInstrBuilder &MIB) { MIB.addImm(AMDGPU::CPol::GLC); } // cpol in selectMUBUFOffsetAtomic()
4362 MIB.addImm(MI.getOperand(OpIdx).getImm() & AMDGPU::CPol::ALL); in renderExtractCPol()
4376 MIB.addImm(MI.getOperand(OpIdx).getImm() | AMDGPU::CPol::GLC); in renderSetGLC()
H A DSIInstrInfo.td822 return CurDAG->getTargetConstant(N->getZExtValue() & AMDGPU::CPol::ALL, SDLoc(N), MVT::i8);
830 return CurDAG->getTargetConstant(N->getZExtValue() | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8);
1114 def CPol : NamedOperandU32<"CPol", NamedMatchClass<"CPol">>;
1115 def CPol_0 : NamedOperandU32Default0<"CPol", NamedMatchClass<"CPol">>;
1116 def CPol_GLC1 : NamedOperandU32Default1<"CPol", NamedMatchClass<"CPol">>;
H A DAMDGPUISelDAGToDAG.cpp2376 SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32); in SelectATOMIC_CMP_SWAP() local
2380 SDValue Ops[] = {CmpVal, VAddr, SRsrc, SOffset, Offset, CPol, in SelectATOMIC_CMP_SWAP()
2394 SDValue CPol = CurDAG->getTargetConstant(AMDGPU::CPol::GLC, SL, MVT::i32); in SelectATOMIC_CMP_SWAP() local
2395 SDValue Ops[] = {CmpVal, SRsrc, SOffset, Offset, CPol, Mem->getChain()}; in SelectATOMIC_CMP_SWAP()
H A DBUFInstructions.td146 offset:$offset, FORMAT:$format, CPol:$cpol, TFE:$tfe, SWZ:$swz),
148 offset:$offset, FORMAT:$format, CPol:$cpol, TFE:$tfe, SWZ:$swz)
152 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
155 SCSrc_b32:$soffset, offset:$offset, FORMAT:$format, CPol:$cpol,
612 (ins SReg_128:$srsrc, SCSrc_b32:$soffset, offset:$offset, CPol:$cpol, SWZ:$swz),
H A DFLATInstructions.td155 !if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
240 (ins flat_offset:$offset, CPol:$cpol)),
279 !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
H A DSIISelLowering.cpp6222 unsigned CPol = cast<ConstantSDNode>( in lowerImage() local
6225 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in lowerImage()
6226 if (CPol & ~AMDGPU::CPol::ALL) in lowerImage()
6243 Ops.push_back(DAG.getTargetConstant(CPol, DL, MVT::i32)); in lowerImage()
6550 unsigned CPol = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); in LowerINTRINSIC_WO_CHAIN() local
6551 if (CPol & ~AMDGPU::CPol::ALL) in LowerINTRINSIC_WO_CHAIN()
11387 MachineOperand &CPol = MI.getOperand(CPolIdx); in AdjustInstrPostInstrSelection() local
11388 CPol.setImm(CPol.getImm() & ~AMDGPU::CPol::GLC); in AdjustInstrPostInstrSelection()
H A DSIInstrInfo.cpp5642 if (const MachineOperand *CPol = in legalizeOperands() local
5644 MIB.addImm(CPol->getImm()); in legalizeOperands()
H A DAMDGPURegisterBankInfo.cpp1733 return CachePolicy & AMDGPU::CPol::ALL; in extractCPol()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4119 unsigned CPol = Inst.getOperand(CPolPos).getImm(); in validateCoherencyBits() local
4123 (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC))) { in validateCoherencyBits()
4128 if (isGFX90A() && (CPol & CPol::SCC)) { in validateCoherencyBits()
4140 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
4145 if (CPol & CPol::GLC) { in validateCoherencyBits()
5487 CPolOn = AMDGPU::CPol::GLC; in parseCPol()
5489 CPolOff = AMDGPU::CPol::GLC; in parseCPol()
5491 CPolOn = AMDGPU::CPol::SLC; in parseCPol()
5493 CPolOff = AMDGPU::CPol::SLC; in parseCPol()
5495 CPolOn = AMDGPU::CPol::DLC; in parseCPol()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp208 if (Imm & CPol::GLC) in printCPol()
210 if (Imm & CPol::SLC) in printCPol()
212 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
214 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
216 if (Imm & ~CPol::ALL) in printCPol()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp551 unsigned CPol = in getInstruction() local
553 AMDGPU::CPol::GLC : 0; in getInstruction()
555 insertNamedMCOperand(MI, MCOperand::createImm(CPol), in getInstruction()
557 } else if (CPol) { in getInstruction()
558 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); in getInstruction()