Searched refs:BaseRegOp (Results 1 – 2 of 2) sorted by relevance
765 const MachineOperand &BaseRegOp = in mergeNarrowZeroStores() local789 .add(BaseRegOp) in mergeNarrowZeroStores()938 const MachineOperand &BaseRegOp = in mergePairedInsns() local1016 MIB.addReg(BaseRegOp.getReg(), RegState::Define); in mergePairedInsns()1020 .add(BaseRegOp) in mergePairedInsns()
3685 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem16Inst() local3686 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem16Inst()3692 unsigned BaseReg = BaseRegOp.getReg(); in expandMem16Inst()3812 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem9Inst() local3813 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem9Inst()3819 unsigned BaseReg = BaseRegOp.getReg(); in expandMem9Inst()