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Searched refs:BaseIdx (Results 1 – 7 of 7) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DPseudoLoweringEmitter.cpp57 unsigned BaseIdx);
74 IndexedMap<OpData> &OperandMap, unsigned BaseIdx) { in addDagOperandMapping() argument
82 OperandMap[BaseIdx + i].Kind = OpData::Reg; in addDagOperandMapping()
83 OperandMap[BaseIdx + i].Data.Reg = DI->getDef(); in addDagOperandMapping()
91 assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!"); in addDagOperandMapping()
93 if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec) { in addDagOperandMapping()
97 Insn.Operands[BaseIdx + i].Rec->getName() + "'"); in addDagOperandMapping()
105 OperandMap[BaseIdx + i + I].Kind = OpData::Operand; in addDagOperandMapping()
108 OperandMap[BaseIdx + i].Kind = OpData::Imm; in addDagOperandMapping()
109 OperandMap[BaseIdx + i].Data.Imm = II->getValue(); in addDagOperandMapping()
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/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
H A DStore.cpp475 SVal BaseIdx = ElemR->getIndex(); in getLValueElement() local
477 if (!BaseIdx.getAs<nonloc::ConcreteInt>()) in getLValueElement()
481 BaseIdx.castAs<nonloc::ConcreteInt>().getValue(); in getLValueElement()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DStackMaps.cpp434 unsigned BaseIdx = GCPtrIndices[P.first]; in parseStatepointOpers() local
436 LLVM_DEBUG(dbgs() << "Base : " << BaseIdx << " Derived : " << DerivedIdx in parseStatepointOpers()
438 (void)parseOperand(MOB + BaseIdx, MOE, Locations, LiveOuts); in parseStatepointOpers()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp1428 Value *BaseIdx = Builder.getInt32(FindIndex(LiveVariables, BasePtrs[i])); in CreateGCRelocates() local
1438 GCRelocateDecl, {StatepointToken, BaseIdx, LiveIdx}, in CreateGCRelocates()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp438 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4; in reservedPrivateSegmentBufferReg() local
439 MCRegister BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx)); in reservedPrivateSegmentBufferReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp4649 SDValue BaseIdx = N->getOperand(1); in PromoteIntRes_EXTRACT_SUBVECTOR() local
4661 SDValue Ops[] = { GetPromotedInteger(InOp0), BaseIdx }; in PromoteIntRes_EXTRACT_SUBVECTOR()
4688 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(), in PromoteIntRes_EXTRACT_SUBVECTOR()
4689 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType())); in PromoteIntRes_EXTRACT_SUBVECTOR()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp6766 unsigned BaseIdx = Op.getConstantOperandVal(2); in getTargetConstantBitsFromNode() local
6767 UndefSrcElts.insertBits(UndefSubElts, BaseIdx); in getTargetConstantBitsFromNode()
6769 EltSrcBits[BaseIdx + i] = EltSubBits[i]; in getTargetConstantBitsFromNode()
6786 unsigned BaseIdx = Op.getConstantOperandVal(1); in getTargetConstantBitsFromNode() local
6787 UndefElts = UndefElts.extractBits(NumSubElts, BaseIdx); in getTargetConstantBitsFromNode()
6788 if ((BaseIdx + NumSubElts) != NumSrcElts) in getTargetConstantBitsFromNode()
6789 EltBits.erase(EltBits.begin() + BaseIdx + NumSubElts, EltBits.end()); in getTargetConstantBitsFromNode()
6790 if (BaseIdx != 0) in getTargetConstantBitsFromNode()
6791 EltBits.erase(EltBits.begin(), EltBits.begin() + BaseIdx); in getTargetConstantBitsFromNode()
7866 int BaseIdx = i * NumBytesPerElt; in getFauxShuffleMask() local
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