Searched refs:BL3 (Results 1 – 1 of 1) sorted by relevance
48 #define BL3 3 macro53 #define BL3 0 macro59 #define OSIOP_SIEN (0x00+BL3) /* rw: SCSI interrupt enable */64 #define OSIOP_SOCL (0x04+BL3) /* rw: SCSI Output Control Latch */69 #define OSIOP_SBCL (0x08+BL3) /* rw: SCSI Bus Control Lines */74 #define OSIOP_SSTAT2 (0x0c+BL3) /* ro: SCSI status reg 2 */81 #define OSIOP_CTEST3 (0x14+BL3) /* ro: Chip test register 3 */86 #define OSIOP_CTEST7 (0x18+BL3) /* rw: Chip test register 7 */93 #define OSIOP_LCRC (0x20+BL3) /* rw: LCRC value */99 #define OSIOP_DCMD (0x24+BL3) /* rw: DMA Command Register */[all …]