Searched refs:ArgRC (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.cpp | 783 const TargetRegisterClass *ArgRC; in passSpecialInputs() local 786 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs() 795 assert(IncomingArgRC == ArgRC); in passSpecialInputs() 800 LI->loadInputValue(InputReg, MIRBuilder, IncomingArg, ArgRC, ArgTy); in passSpecialInputs() 819 const TargetRegisterClass *ArgRC; in passSpecialInputs() local 822 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs() 825 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs() 828 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs()
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| H A D | AMDGPULegalizerInfo.h | 95 const TargetRegisterClass *ArgRC, LLT ArgTy) const;
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| H A D | AMDGPULegalizerInfo.cpp | 2722 const TargetRegisterClass *ArgRC, in loadInputValue() argument 2728 Register LiveIn = getFunctionLiveInPhysReg(B.getMF(), B.getTII(), SrcReg, *ArgRC, in loadInputValue() 2756 const TargetRegisterClass *ArgRC; in loadInputValue() local 2758 std::tie(Arg, ArgRC, ArgTy) = MFI->getPreloadedValue(ArgType); in loadInputValue() 2762 return loadInputValue(DstReg, B, Arg, ArgRC, ArgTy); in loadInputValue()
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| H A D | SIISelLowering.cpp | 2722 const TargetRegisterClass *ArgRC; in passSpecialInputs() local 2725 std::tie(OutgoingArg, ArgRC, ArgTy) = in passSpecialInputs() 2735 assert(IncomingArgRC == ArgRC); in passSpecialInputs() 2738 EVT ArgVT = TRI->getSpillSize(*ArgRC) == 8 ? MVT::i64 : MVT::i32; in passSpecialInputs() 2742 InputReg = loadInputValue(DAG, ArgRC, ArgVT, DL, *IncomingArg); in passSpecialInputs() 2766 const TargetRegisterClass *ArgRC; in passSpecialInputs() local 2769 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs() 2772 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs() 2775 std::tie(OutgoingArg, ArgRC, Ty) = in passSpecialInputs() 2792 InputReg = loadInputValue(DAG, ArgRC, MVT::i32, DL, *IncomingArgX); in passSpecialInputs() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 16037 const TargetRegisterClass *ArgRC = in canMergeExpensiveCrossRegisterBankCopy() local 16040 if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT)) in canMergeExpensiveCrossRegisterBankCopy() 16048 if (!TRI || TRI->getCommonSubClass(ArgRC, ResRC)) in canMergeExpensiveCrossRegisterBankCopy()
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