| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 35 unsigned AndOpc; member in __anonb4c9c4b40111::SIOptimizeExecMaskingPreRA
134 if (!And || And->getOpcode() != AndOpc || in optimizeVcndVcmpPair()
270 if (I->getOpcode() == AndOpc && I->getOperand(0).getReg() == DstReg && in optimizeElseBranch()
315 AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64; in runOnMachineFunction()
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| H A D | SILowerControlFlow.cpp | 78 unsigned AndOpc; member in __anonfe9ad85c0111::SILowerControlFlow
234 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp) in emitIf()
314 MachineInstr *And = BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg) in emitElse()
377 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
783 AndOpc = AMDGPU::S_AND_B32; in runOnMachineFunction()
793 AndOpc = AMDGPU::S_AND_B64; in runOnMachineFunction()
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| H A D | SIWholeQuadMode.cpp | 162 unsigned AndOpc; member in __anon35eed8a90111::SIWholeQuadMode
970 NewTerm = BuildMI(MBB, MI, DL, TII->get(AndOpc), Exec) in lowerKillI1()
979 NewTerm = BuildMI(MBB, &MI, DL, TII->get(AndOpc), Exec) in lowerKillI1()
983 unsigned Opcode = KillVal ? AndN2Opc : AndOpc; in lowerKillI1()
1150 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AndOpc), Exec) in toExact()
1523 AndOpc = AMDGPU::S_AND_B32; in runOnMachineFunction()
1531 AndOpc = AMDGPU::S_AND_B64; in runOnMachineFunction()
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| H A D | AMDGPUInstructionSelector.cpp | 156 unsigned AndOpc = in selectCOPY() local
158 BuildMI(*BB, &I, DL, TII.get(AndOpc), MaskedReg) in selectCOPY()
1908 unsigned AndOpc = IsVALU ? AMDGPU::V_AND_B32_e64 : AMDGPU::S_AND_B32; in selectG_TRUNC() local
1913 BuildMI(*MBB, I, DL, TII.get(AndOpc), TmpReg1) in selectG_TRUNC()
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| H A D | SIInstrInfo.cpp | 5140 unsigned AndOpc = in emitLoadSRsrcFromVGPRLoop() local
5194 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndReg) in emitLoadSRsrcFromVGPRLoop()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InstructionSelector.cpp | 799 unsigned AndOpc; in selectZext() local
801 AndOpc = X86::AND8ri; in selectZext()
803 AndOpc = X86::AND16ri8; in selectZext()
805 AndOpc = X86::AND32ri8; in selectZext()
807 AndOpc = X86::AND64ri8; in selectZext()
827 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg) in selectZext()
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