Searched refs:AddrDef (Results 1 – 2 of 2) sorted by relevance
3582 auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI); in selectGlobalSAddr() local3583 if (!AddrDef) in selectGlobalSAddr()3587 if (AddrDef->MI->getOpcode() == AMDGPU::G_PTR_ADD) { in selectGlobalSAddr()3590 getSrcRegIgnoringCopies(AddrDef->MI->getOperand(1).getReg(), *MRI); in selectGlobalSAddr()3593 Register PtrBaseOffset = AddrDef->MI->getOperand(2).getReg(); in selectGlobalSAddr()3613 if (AddrDef->MI->getOpcode() == AMDGPU::G_IMPLICIT_DEF || in selectGlobalSAddr()3614 AddrDef->MI->getOpcode() == AMDGPU::G_CONSTANT || !isSGPR(AddrDef->Reg)) in selectGlobalSAddr()3627 [=](MachineInstrBuilder &MIB) { MIB.addReg(AddrDef->Reg); }, // saddr in selectGlobalSAddr()3651 auto AddrDef = getDefSrcRegIgnoringCopies(Addr, *MRI); in selectScratchSAddr() local3652 if (!AddrDef) in selectScratchSAddr()[all …]
831 MachineInstr *AddrDef = getOpcodeDef(TargetOpcode::G_PTR_ADD, Addr, MRI); in findPreIndexCandidate() local832 if (!AddrDef || MRI.hasOneNonDBGUse(Addr)) in findPreIndexCandidate()835 Base = AddrDef->getOperand(1).getReg(); in findPreIndexCandidate()836 Offset = AddrDef->getOperand(2).getReg(); in findPreIndexCandidate()912 MachineInstr &AddrDef = *MRI.getUniqueVRegDef(MatchInfo.Addr); in applyCombineIndexedLoadStore() local947 AddrDef.eraseFromParent(); in applyCombineIndexedLoadStore()