| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86InsertPrefetch.cpp | 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg(); in IsMemOpCompatibleWithPrefetch()
217 static_assert(X86::AddrBaseReg == 0 && X86::AddrScaleAmt == 1 && in runOnMachineFunction()
225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg()) in runOnMachineFunction()
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| H A D | X86OptimizeLEAs.cpp | 194 return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg), in getMemOpKey()
365 if (TII->getRegClass(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) != in chooseBestLEA()
460 if (!isIdenticalOp(MI.getOperand(MemOpNo + X86::AddrBaseReg), MO)) in isReplaceable()
466 if (i != (unsigned)(MemOpNo + X86::AddrBaseReg) && in isReplaceable()
561 MI.getOperand(MemOpNo + X86::AddrBaseReg) in removeRedundantAddrCalc()
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| H A D | X86AsmPrinter.cpp | 288 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintLeaMemReference()
325 PrintModifiedOperand(MI, OpNo + X86::AddrBaseReg, O, Modifier); in PrintLeaMemReference()
353 const MachineOperand &BaseReg = MI->getOperand(OpNo + X86::AddrBaseReg); in PrintIntelMemReference()
375 PrintOperand(MI, OpNo + X86::AddrBaseReg, O); in PrintIntelMemReference()
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| H A D | X86FixupLEAs.cpp | 372 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in optTwoAddrLEA()
467 MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg); in processInstruction()
504 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstructionForSlowLEA()
556 const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg); in processInstrForSlow3OpLEA()
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| H A D | X86CallFrameOptimization.cpp | 427 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
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| H A D | X86SpeculativeLoadHardening.cpp | 1338 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1412 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in tracePredStateThroughBlocksAndHarden()
1814 UseMI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in sinkPostLoadHardenedInst()
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| H A D | X86InstrInfo.h | 114 MI.getOperand(Op + X86::AddrBaseReg).isReg() && in isLeaMem()
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| H A D | X86AvoidStoreForwardingBlocks.cpp | 301 return MI->getOperand(AddrOffset + X86::AddrBaseReg); in getBaseOperand()
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| H A D | X86LoadValueInjectionLoadHardening.cpp | 787 MI.getOperand(MemRefBeginIdx + X86::AddrBaseReg); in instrUsesRegToAccessMemory()
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| H A D | X86InstrInfo.cpp | 679 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() && in isFrameOperand()
686 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex(); in isFrameOperand()
1085 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() && in isReallyTriviallyReMaterializable()
1090 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
1110 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg()) in isReallyTriviallyReMaterializable()
1112 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg(); in isReallyTriviallyReMaterializable()
3678 auto &BaseOp = MemI.getOperand(MemRefBegin + X86::AddrBaseReg); in getAddrModeFromMemoryOp()
3747 &MemOp.getOperand(MemRefBegin + X86::AddrBaseReg); in getMemOperandsWithOffsetWidth()
6727 if (!HasSameOp(X86::AddrBaseReg) || !HasSameOp(X86::AddrScaleAmt) || in areLoadsFromSameBasePtr()
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| H A D | X86MCInstLower.cpp | 382 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() && in SimplifyShortMoveForm()
406 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 || in SimplifyShortMoveForm()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCCodeEmitter.cpp | 163 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in is16BitMemOperand()
183 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is32BitMemOperand()
205 const MCOperand &BaseReg = MI.getOperand(Op + X86::AddrBaseReg); in is64BitMemOperand()
386 const MCOperand &Base = MI.getOperand(Op + X86::AddrBaseReg); in emitMemModRMByte()
901 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
948 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
964 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
981 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1008 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); in emitVEXOpcodePrefix()
1261 REX |= isREXExtendedReg(MI, MemOperand + X86::AddrBaseReg) << 0; // REX.B in emitREXPrefix()
[all …]
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| H A D | X86IntelInstPrinter.cpp | 355 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference()
367 printOperand(MI, Op+X86::AddrBaseReg, O); in printMemReference()
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| H A D | X86ATTInstPrinter.cpp | 398 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
419 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
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| H A D | X86AsmBackend.cpp | 349 unsigned BaseRegNum = MemoryOperand + CurOp + X86::AddrBaseReg; in isRIPRelative()
425 unsigned BaseRegNum = MemoryOperand + X86::AddrBaseReg; in determinePaddingPrefix()
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| H A D | X86BaseInfo.h | 32 AddrBaseReg = 0, enumerator
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| H A D | X86MCTargetDesc.cpp | 543 const MCOperand &BaseReg = Inst.getOperand(MemOpStart + X86::AddrBaseReg); in evaluateMemoryOperandAddress()
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