Home
last modified time | relevance | path

Searched refs:ADDiu (Results 1 – 24 of 24) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp35 AddInstr(SeqLs, Inst(ADDiu, Imm & 0xffffULL)); in GetInstSeqLsADDiu()
61 AddInstr(SeqLs, Inst(ADDiu, MaskedImm)); in GetInstSeqLs()
92 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi()
134 ADDiu = Mips::ADDiu; in Analyze()
139 ADDiu = Mips::DADDiu; in Analyze()
H A DMipsInstructionSelector.cpp163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)}) in materialize32BitImm()
354 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
692 MachineInstr *ADDiu = in select() local
693 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
697 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); in select()
698 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
711 MachineInstr *ADDiu = in select() local
712 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
716 ADDiu->getOperand(2).setTargetFlags(MipsII::MO_ABS_LO); in select()
717 if (!constrainSelectedInstRegOperands(*ADDiu, TII, TRI, RBI)) in select()
[all …]
H A DMipsMachineFunction.cpp103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1) in initGlobalBaseReg()
H A DMipsAnalyzeImmediate.h60 unsigned ADDiu, ORi, SLL, LUi; variable
H A DMipsBranchExpansion.cpp465 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
526 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
534 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
735 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
H A DMipsInstrInfo.td123 // target constant nodes that would otherwise remain unchanged with ADDiu
2024 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16_relaxed, GPR32Opnd,
2795 defm : OneOrTwoOperandMacroImmediateAlias<"addu", ADDiu>, ISA_MIPS1;
2874 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
2876 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
3132 defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>, ISA_MIPS1;
3142 (ADDiu GPR32:$src, imm:$imm)>, ISA_MIPS1, ASE_NOT_DSP;
3208 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>, ISA_MIPS1;
3219 (ADDiu GPR32:$gp, tglobaladdr:$in)>, ISA_MIPS1, ABI_NOT_N64;
3221 (ADDiu GPR32:$gp, tconstpool:$in)>, ISA_MIPS1, ABI_NOT_N64;
[all …]
H A DRelocation.txt65 defm : MipsHiLoRelocs<LUi, ADDiu, ZERO, GPR32Opnd>;
H A DMipsMCInstLower.cpp306 lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu); in lowerLongBranch()
H A DMicroMipsSizeReduction.cpp214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
H A DMipsSEISelDAGToDAG.cpp88 if ((MI.getOpcode() == Mips::ADDiu) && in replaceUsesWithZeroReg()
146 BuildMI(MBB, &MI, MI.getDebugLoc(), TII->get(Mips::ADDiu)) in emitMCountABI()
1113 const unsigned ADDiuOp = Is32BitSplat ? Mips::ADDiu : Mips::DADDiu; in trySelect()
H A DMipsFastISel.cpp368 unsigned Opc = Mips::ADDiu; in materialize32BitInt()
427 emitInst(Mips::ADDiu, TempReg) in materializeGV()
742 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); in emitCmp()
743 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); in emitCmp()
H A DMipsSEFrameLowering.cpp418 unsigned ADDiu = ABI.GetPtrAddiuOp(); in emitPrologue() local
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO).addImm(MaxAlign); in emitPrologue()
H A DMipsSEInstrInfo.cpp594 unsigned ADDiu = ABI.GetPtrAddiuOp(); in adjustStackPtr() local
601 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); in adjustStackPtr()
H A DMipsInstrInfo.cpp884 case Mips::ADDiu: in isAddImmediate()
H A DMipsAsmPrinter.cpp1230 MCInstBuilder(Mips::ADDiu) in EmitSled()
H A DMipsSEISelLowering.cpp3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
3137 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) in emitMSACBranchPseudo()
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) in emitMSACBranchPseudo()
H A DMipsDSPInstrInfo.td1401 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR)),
1409 (ValTy (COPY_TO_REGCLASS (ADDiu ZERO, -1), DSPR))))>;
H A DMipsScheduleP5600.td224 def : InstRW<[P5600WriteEitherALU], (instrs ADD, ADDi, ADDiu, ANDi, ORi, ROTR,
H A DMipsScheduleGeneric.td47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
H A DMips64InstrInfo.td910 (ADDiu GPR32:$src, immSExt16:$imm16), sub_32)>;
H A DMipsISelLowering.cpp1964 BuildMI(BB, DL, TII->get(ArePtrs64bit ? Mips::DADDiu : Mips::ADDiu), MaskLSB2) in emitAtomicCmpSwapPartword()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp102 return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu; in GetPtrAddiuOp()
H A DMipsTargetStreamer.cpp1176 TmpInst.setOpcode(Mips::ADDiu); in emitDirectiveCpLoad()
1259 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(), in emitDirectiveCpsetup()
1276 emitRRX(Mips::ADDiu, GPReg, GPReg, MCOperand::createExpr(LoExpr), SMLoc(), in emitDirectiveCpsetup()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2552 case Mips::ADDiu: case Mips::ADDiu_MM: in tryExpandInstruction()
2751 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI); in loadImmediate()
3001 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3068 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in loadAndAddSymbolAddress()
3207 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr), in loadAndAddSymbolAddress()
3481 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg, in expandLoadDoubleImmToGPR()
4302 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
4313 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI); in expandDivRem()
4785 case Mips::ADDiu: in expandAliasImmediate()
5414 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; in expandSeqI()
[all …]