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/minix3/external/bsd/llvm/dist/llvm/test/MC/Mips/
H A Dmips64-register-names-o32.s5 # Second byte of daddiu with $zero at rt contains the number of the source
9 daddiu $zero, $zero, 0 # CHECK: encoding: [0x64,0x00,0x00,0x00]
10 daddiu $at, $zero, 0 # CHECK: encoding: [0x64,0x01,0x00,0x00]
11 daddiu $v0, $zero, 0 # CHECK: encoding: [0x64,0x02,0x00,0x00]
12 daddiu $v1, $zero, 0 # CHECK: encoding: [0x64,0x03,0x00,0x00]
13 daddiu $a0, $zero, 0 # CHECK: encoding: [0x64,0x04,0x00,0x00]
14 daddiu $a1, $zero, 0 # CHECK: encoding: [0x64,0x05,0x00,0x00]
15 daddiu $a2, $zero, 0 # CHECK: encoding: [0x64,0x06,0x00,0x00]
16 daddiu $a3, $zero, 0 # CHECK: encoding: [0x64,0x07,0x00,0x00]
17 daddiu $t0, $zero, 0 # CHECK: encoding: [0x64,0x08,0x00,0x00]
[all …]
H A Dmips-register-names-o32.s4 # Second byte of addiu with $zero at rt contains the number of the source
8 addiu $zero, $zero, 0 # CHECK: encoding: [0x24,0x00,0x00,0x00]
9 addiu $at, $zero, 0 # CHECK: encoding: [0x24,0x01,0x00,0x00]
10 addiu $v0, $zero, 0 # CHECK: encoding: [0x24,0x02,0x00,0x00]
11 addiu $v1, $zero, 0 # CHECK: encoding: [0x24,0x03,0x00,0x00]
12 addiu $a0, $zero, 0 # CHECK: encoding: [0x24,0x04,0x00,0x00]
13 addiu $a1, $zero, 0 # CHECK: encoding: [0x24,0x05,0x00,0x00]
14 addiu $a2, $zero, 0 # CHECK: encoding: [0x24,0x06,0x00,0x00]
15 addiu $a3, $zero, 0 # CHECK: encoding: [0x24,0x07,0x00,0x00]
16 addiu $t0, $zero, 0 # CHECK: encoding: [0x24,0x08,0x00,0x00]
[all …]
H A Dmips64-register-names-n32-n64.s10 # Second byte of addiu with $zero at rt contains the number of the source
14 daddiu $zero, $zero, 0 # CHECK: encoding: [0x64,0x00,0x00,0x00]
15 daddiu $at, $zero, 0 # CHECK: encoding: [0x64,0x01,0x00,0x00]
16 daddiu $v0, $zero, 0 # CHECK: encoding: [0x64,0x02,0x00,0x00]
17 daddiu $v1, $zero, 0 # CHECK: encoding: [0x64,0x03,0x00,0x00]
18 daddiu $a0, $zero, 0 # CHECK: encoding: [0x64,0x04,0x00,0x00]
19 daddiu $a1, $zero, 0 # CHECK: encoding: [0x64,0x05,0x00,0x00]
20 daddiu $a2, $zero, 0 # CHECK: encoding: [0x64,0x06,0x00,0x00]
21 daddiu $a3, $zero, 0 # CHECK: encoding: [0x64,0x07,0x00,0x00]
22 daddiu $a4, $zero, 0 # CHECK: encoding: [0x64,0x08,0x00,0x00]
[all …]
H A Dmips-control-instructions.s20 # CHECK32: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
21 # CHECK32: teq $zero, $3, 1 # encoding: [0x00,0x03,0x00,0x74]
23 # CHECK32: tge $zero, $3 # encoding: [0x00,0x03,0x00,0x30]
24 # CHECK32: tge $zero, $3, 3 # encoding: [0x00,0x03,0x00,0xf0]
26 # CHECK32: tgeu $zero, $3 # encoding: [0x00,0x03,0x00,0x31]
27 # CHECK32: tgeu $zero, $3, 7 # encoding: [0x00,0x03,0x01,0xf1]
29 # CHECK32: tlt $zero, $3 # encoding: [0x00,0x03,0x00,0x32]
30 # CHECK32: tlt $zero, $3, 31 # encoding: [0x00,0x03,0x07,0xf2]
32 # CHECK32: tltu $zero, $3 # encoding: [0x00,0x03,0x00,0x33]
33 # CHECK32: tltu $zero, $3, 255 # encoding: [0x00,0x03,0x3f,0xf3]
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A Dvector-shuffle-128-v16.ll321 ; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,…
322 …SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
328 ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,…
329 …SSE41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
335 ; AVX-NEXT: vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[3,2,1,0,7,6,5,4]
336 ; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[3,2,1,0,7,6,5,4],zero,zero,zero,zero,zero,zero,zero,zero
365 ; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[15,14,13,12],zero,zero,zero,zero,x…
366 …E3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0],zero,zero,zero,zero,xmm0[11,10,9,8],zero,zero,zer…
372 ; SSE41-NEXT: pshufb {{.*#+}} xmm1 = zero,zero,zero,zero,xmm1[15,14,13,12],zero,zero,zero,zero,x…
373 …41-NEXT: pshufb {{.*#+}} xmm0 = xmm0[3,2,1,0],zero,zero,zero,zero,xmm0[11,10,9,8],zero,zero,zer…
[all …]
H A Dpalignr.ll89 …YONAH-NEXT: psrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
90 ; CHECK-YONAH-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm…
106 …: psrldq {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,z…
107 ; CHECK-YONAH-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7,8,…
123 …CK-YONAH-NEXT: psrldq {{.*#+}} xmm0 = xmm0[5,6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero
124 ; CHECK-YONAH-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zer…
145 ; CHECK-YONAH-NEXT: psrldq {{.*#+}} xmm0 = xmm0[2,3,4,5,6,7,8,9,10,11,12,13,14,15],zero,zero
146 …ECK-YONAH-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,z…
H A Dvector-shuffle-128-v8.ll1396 ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
1403 ; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11,12,13]
1415 ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,…
1422 ; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2…
1433 ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,z…
1439 ; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,…
1451 ; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
1458 ; AVX-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9,10,11]
1468 …: psrldq {{.*#+}} xmm1 = xmm1[10,11,12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,z…
1469 ; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7,8,9]
[all …]
H A Dvector-shuffle-256-v32.ll317 … AVX1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero…
318 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0,0],zero
342 …1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zer…
343 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0]
366 …1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zer…
367 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0]
390 …1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm…
391 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0]
414 …1-NEXT: vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[4],…
415 ; AVX1-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,0,0,0,0,0,0,0,0,0,0],zero,xmm0[0,0,0,0]
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/
H A Ddivrem.ll8 ; RUN: llc -march=mips -mcpu=mips32 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
9 ; RUN: llc -march=mips -mcpu=mips32r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
10 ; RUN: llc -march=mips -mcpu=mips32r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
11 ; RUN: llc -march=mips64 -mcpu=mips64 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
12 ; RUN: llc -march=mips64 -mcpu=mips64r2 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
13 ; RUN: llc -march=mips64 -mcpu=mips64r6 -mno-check-zero-division < %s | FileCheck %s -check-prefix=…
25 ; NOCHECK - Division by zero will not be detected
34 ; ACC32: div $zero, $4, $5
35 ; ACC32-TRAP: teq $5, $zero, 7
37 ; ACC64: div $zero, $4, $5
[all …]
H A Dfcmp.ll18 ; ALL: addiu $2, $zero, 0
28 ; 32-C-DAG: addiu $2, $zero, 1
30 ; 32-C: movf $2, $zero, $fcc0
32 ; 64-C-DAG: addiu $2, $zero, 1
34 ; 64-C: movf $2, $zero, $fcc0
52 ; 32-C-DAG: addiu $2, $zero, 1
54 ; 32-C: movt $2, $zero, $fcc0
56 ; 64-C-DAG: addiu $2, $zero, 1
58 ; 64-C: movt $2, $zero, $fcc0
76 ; 32-C-DAG: addiu $2, $zero, 1
[all …]
H A Dcmov.ll126 ; 32-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
136 ; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
196 ; 32-CMOV-DAG: addiu $[[R0:[0-9]+]], $zero, 234
214 ; 64-CMOV: addiu $[[R0:[0-9]+]], $zero, 234
240 ; 32-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
241 ; 32-CMOV-DAG: addiu $[[I5:2]], $zero, 5
245 ; 32-CMP-DAG: addiu $[[I3:[0-9]+]], $zero, 3
246 ; 32-CMP-DAG: addiu $[[I5:[0-9]+]], $zero, 5
253 ; 64-CMOV-DAG: addiu $[[I3:[0-9]+]], $zero, 3
254 ; 64-CMOV-DAG: addiu $[[I5:2]], $zero, 5
[all …]
H A Do32_cc.ll57 ; ALL-DAG: addiu $4, $zero, 12
58 ; ALL-DAG: addiu $5, $zero, 13
59 ; ALL-DAG: addiu $6, $zero, 14
60 ; ALL-DAG: addiu $7, $zero, 15
72 ; ALL-DAG: addiu $6, $zero, 23
86 ; ALL-DAG: addiu $6, $zero, 33
87 ; ALL-DAG: addiu $7, $zero, 24
99 ; ALL-DAG: addiu $5, $zero, 43
100 ; ALL-DAG: addiu $6, $zero, 34
111 ; ALL-DAG: addiu $4, $zero, 22
[all …]
/minix3/lib/libc/compat/arch/alpha/gen/
H A Dcompat_setjmp.S64 mov zero, a0
69 mov zero, a0
99 stq zero, (70 * 8)(a0) /* FP software control XXX */
100 stq zero, (71 * 8)(a0) /* sc_reserved[0] */
101 stq zero, (72 * 8)(a0) /* sc_reserved[1] */
102 stq zero, (73 * 8)(a0) /* sc_xxx[0] */
103 stq zero, (74 * 8)(a0) /* sc_xxx[1] */
104 stq zero, (75 * 8)(a0) /* sc_xxx[2] */
105 stq zero, (76 * 8)(a0) /* sc_xxx[3] */
106 stq zero, (77 * 8)(a0) /* sc_xxx[4] */
[all …]
H A Dcompat__setjmp.S72 stq zero, (70 * 8)(a0) /* FP software control XXX */
73 stq zero, (71 * 8)(a0) /* sc_reserved[0] */
74 stq zero, (72 * 8)(a0) /* sc_reserved[1] */
75 stq zero, (73 * 8)(a0) /* sc_xxx[0] */
76 stq zero, (74 * 8)(a0) /* sc_xxx[1] */
77 stq zero, (75 * 8)(a0) /* sc_xxx[2] */
78 stq zero, (76 * 8)(a0) /* sc_xxx[3] */
79 stq zero, (77 * 8)(a0) /* sc_xxx[4] */
80 stq zero, (78 * 8)(a0) /* sc_xxx[5] */
81 stq zero, (79 * 8)(a0) /* sc_xxx[6] */
[all …]
/minix3/lib/libm/noieee_src/
H A Dn_pow.c121 static const double zero=0.0, one=1.0, two=2.0, negone= -1.0; variable
142 if (y==zero) in pow()
152 return ((y<0)? zero : ((x<zero)? y-y : y)); in pow()
154 return ((y>0)? zero : ((x<0)? y-y : -y)); in pow()
165 else if ( (t=drem(y,two)) == zero) in pow()
173 else if (x==zero) /* x is -0 */ in pow()
174 return ((y>zero)? -x : one/(-x)); in pow()
176 return (zero/zero); in pow()
188 if (x == zero) { in pow_P()
189 if (y > zero) in pow_P()
[all …]
/minix3/lib/libc/arch/alpha/gen/
H A D__setjmp14.S66 mov zero, a0 /* how (insignificant) */
67 mov zero, a1 /* set (NULL) */
72 mov zero, a0
104 stq zero, SC_FP_CONTROL(a0) /* FP software control XXX */
105 stq zero, (SC_RESERVED + 0*8)(a0) /* sc_reserved[0] */
106 stq zero, (SC_RESERVED + 1*8)(a0) /* sc_reserved[1] */
107 stq zero, (SC_XXX + 0*8)(a0) /* sc_xxx[0] */
108 stq zero, (SC_XXX + 1*8)(a0) /* sc_xxx[1] */
109 stq zero, (SC_XXX + 2*8)(a0) /* sc_xxx[2] */
110 stq zero, (SC_XXX + 3*8)(a0) /* sc_xxx[3] */
[all …]
/minix3/external/bsd/llvm/dist/clang/test/CXX/basic/basic.lookup/basic.lookup.qual/namespace.qual/
H A Dp2.cpp4 int zero = 0; // expected-note {{candidate found by name lookup is 'Ints::zero'}} variable
10 float zero = 0.0f; // expected-note {{candidate found by name lookup is 'Floats::zero'}} variable
21 int i = Ints::zero; in test()
24 float f = Floats::zero; in test()
27 double n = Numbers::zero; // expected-error {{reference to 'zero' is ambiguous}} in test()
38 Number zero(0.0f); variable
43 Numbers::Number n = Numbers::zero; in test2()
54 Numbers::Number n = Numbers::zero; in test3()
58 int i = Ints::zero; in test3()
62 float f = Floats::zero; in test3()
/minix3/lib/libm/src/
H A Dk_standard.c31 static const double zero = 0.0; /* used as const */ variable
105 exc.retval = zero; in __kernel_standard()
107 exc.retval = zero/zero; in __kernel_standard()
121 exc.retval = zero; in __kernel_standard()
123 exc.retval = zero/zero; in __kernel_standard()
139 exc.retval = zero; in __kernel_standard()
141 exc.retval = copysign(signbit(y) ? M_PI : zero, x); in __kernel_standard()
199 exc.retval = zero; in __kernel_standard()
373 exc.retval = zero/zero; in __kernel_standard()
409 exc.retval = zero/zero; in __kernel_standard()
[all …]
/minix3/lib/libc/arch/mips/gen/
H A Dldexp.S70 beq t1, zero, 1f # zero or denormalized number?
75 ble t1, zero, 4f # underflow?
83 bne t2, zero, 1f
84 beq t3, zero, 9f # result is zero
90 move t9, zero
91 bne t2, zero, 1f
96 bne ta0, zero, 1f
101 bne ta0, zero, 1f
106 bne ta0, zero, 1f
111 bne ta0, zero, 1f
[all …]
/minix3/common/lib/libc/arch/alpha/string/
H A Dbzero.S37 subq zero,a0,t0
49 lda t0,-1(zero) /* t0=-1 */
73 stq zero,0(a0)
74 stq zero,8(a0)
75 stq zero,16(a0)
76 stq zero,24(a0)
78 stq zero,32(a0)
79 stq zero,40(a0)
80 stq zero,48(a0)
81 stq zero,56(a0)
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Generic/
H A Dzero-sized-array.ll4 %zero = type [0 x i8]
5 %foobar = type { i32, %zero }
10 call i32 @f2(%zero %arg2, i32 5, i32 42)
14 define i32 @f2(%zero %x, i32 %y, i32 %z) {
18 define void @f3(%zero %x, i32 %y) {
19 call i32 @f2(%zero %x, i32 5, i32 %y)
23 define void @f4(%zero %z) {
24 insertvalue %foobar undef, %zero %z, 1
34 %insert120 = insertvalue %foobar undef, %zero %y, 1
38 define void @f6(%zero %x, %zero %y) {
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/MC/Mips/mips3/
H A Dvalid.s70 ddiv $zero,$k0,$s3
71 ddivu $zero,$s0,$s1
72 div $zero,$25,$11
75 divu $zero,$25,$15
80 …dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0x…
81 …dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0x…
82 …dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
83 …dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0x…
84 …dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0x…
85 …dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x…
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/Mips/llvm-ir/
H A Dsrem.ll25 ; NOT-R6: div $zero, $4, $5
26 ; NOT-R6: teq $5, $zero, 7
32 ; R6: teq $5, $zero, 7
44 ; NOT-R2-R6: div $zero, $4, $5
45 ; NOT-R2-R6: teq $5, $zero, 7
50 ; R2: div $zero, $4, $5
51 ; R2: teq $5, $zero, 7
56 ; R6: teq $5, $zero, 7
67 ; NOT-R2-R6: div $zero, $4, $5
68 ; NOT-R2-R6: teq $5, $zero, 7
[all …]
H A Dudiv.ll24 ; NOT-R6: divu $zero, $4, $5
25 ; NOT-R6: teq $5, $zero, 7
29 ; R6: teq $5, $zero, 7
39 ; NOT-R6: divu $zero, $4, $5
40 ; NOT-R6: teq $5, $zero, 7
44 ; R6: teq $5, $zero, 7
54 ; NOT-R6: divu $zero, $4, $5
55 ; NOT-R6: teq $5, $zero, 7
59 ; R6: teq $5, $zero, 7
69 ; NOT-R6: divu $zero, $4, $5
[all …]
H A Dsdiv.ll24 ; NOT-R6: div $zero, $4, $5
25 ; NOT-R6: teq $5, $zero, 7
32 ; R6: teq $5, $zero, 7
45 ; NOT-R2-R6: div $zero, $4, $5
46 ; NOT-R2-R6: teq $5, $zero, 7
52 ; R2: div $zero, $4, $5
53 ; R2: teq $5, $zero, 7
59 ; R6: teq $5, $zero, 7
71 ; NOT-R2-R6: div $zero, $4, $5
72 ; NOT-R2-R6: teq $5, $zero, 7
[all …]

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