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Searched refs:writeback (Results 1 – 19 of 19) sorted by relevance

/minix3/external/bsd/llvm/dist/clang/lib/CodeGen/
H A DCGCall.h93 Writeback writeback; in addWriteback() local
94 writeback.Source = srcLV; in addWriteback()
95 writeback.Temporary = temporary; in addWriteback()
96 writeback.ToUse = toUse; in addWriteback()
97 Writebacks.push_back(writeback); in addWriteback()
H A DCGCall.cpp2407 const CallArgList::Writeback &writeback) { in emitWriteback() argument
2408 const LValue &srcLV = writeback.Source; in emitWriteback()
2428 llvm::Value *value = CGF.Builder.CreateLoad(writeback.Temporary); in emitWriteback()
2442 if (writeback.ToUse) { in emitWriteback()
2450 CGF.EmitARCIntrinsicUse(writeback.ToUse); in emitWriteback()
/minix3/external/bsd/llvm/dist/llvm/test/MC/ARM/
H A Dthumb-diagnostics.s58 @ Invalid writeback and register lists for LDM
74 @ CHECK-ERRORS: error: writeback operator '!' expected
77 @ CHECK-ERRORS: error: writeback operator '!' not allowed when base register in register list
80 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
83 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
108 @ Invalid writeback and register lists for PUSH/POP
119 @ Invalid writeback and register lists for STM
134 @ CHECK-ERRORS-V8: error: writeback operator '!' not allowed when base register in register list
137 @ CHECK-ERRORS-V8: error: writeback register not allowed in register list
H A Ddiagnostics.s460 @ CHECK-ERRORS: error: writeback register not allowed in register list
461 @ CHECK-ERRORS: error: writeback register not allowed in register list
462 @ CHECK-ERRORS: error: writeback register not allowed in register list
463 @ CHECK-ERRORS: error: writeback register not allowed in register list
484 @ CHECK-ERRORS: error: system STM cannot have writeback register
485 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
H A Darm-load-store-multiple-deprecated.s204 @ CHECK-V7: error: writeback register not allowed in register list
207 @ CHECK-V7: error: writeback register not allowed in register list
/minix3/external/bsd/llvm/dist/llvm/test/MC/AArch64/
H A Darm64-diags.s155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
182 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
185 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
188 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
191 ; CHECK-ERRORS: error: unpredictable LDP instruction, writeback base is also a destination
224 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
227 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
230 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
233 ; CHECK-ERRORS: error: unpredictable LDR instruction, writeback base is also a source
236 ; CHECK-ERRORS: error: unpredictable STR instruction, writeback base is also a source
[all …]
/minix3/external/bsd/llvm/dist/llvm/test/MC/Disassembler/AArch64/
H A Dbasic-a64-unpredictable.txt84 # Also unpredictable if writeback clashes with either transfer register
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td61 // consumes the pipe for one cycle at issue and another cycle at writeback.
90 // but only consume the pipe for one cycle at issue and a cycle at writeback.
203 // The ID pipe is consumed for 2 cycles: issue and writeback.
210 // The ID pipe is consumed for 2 cycles: issue and writeback.
626 // Only the first WriteVLD and WriteAdr for writeback matches def operands.
767 // Only the WriteAdr for writeback matches a def operands.
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1528 bool writeback = (P == 0) || (W == 1); in DecodeAddrMode2IdxInstruction() local
1530 if (P && writeback) in DecodeAddrMode2IdxInstruction()
1532 else if (!P && writeback) in DecodeAddrMode2IdxInstruction()
1535 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode2IdxInstruction()
1635 bool writeback = (W == 1) | (P == 0); in DecodeAddrMode3Instruction() local
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1671 if (writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
1688 if (!type && writeback && Rn == 15) in DecodeAddrMode3Instruction()
1690 if (writeback && (Rn == Rt || Rn == Rt2)) in DecodeAddrMode3Instruction()
1705 if (!type && writeback && (Rn == 15 || Rn == Rt)) in DecodeAddrMode3Instruction()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA9.td448 // register file writeback!).
2313 // A9WriteAdr consumes AGU regardless address writeback. But it's
2323 // Store either has no def operands, or the one def for address writeback.
2341 // Load multiple with address writeback has an extra def operand in
2345 // resources are identical, For stores only the address writeback
2360 // Note: Unlike VLDM, VLD1 expects the writeback operand after the
2381 // address writeback.
H A DARMInstrNEON.td698 // ...with address register writeback:
854 // ...with address register writeback:
927 // ...with address register writeback:
986 // ...with address register writeback:
1111 // ...with address register writeback:
1174 // ...with address register writeback:
1245 // ...with address register writeback:
1322 // ...with address register writeback:
1409 // ...with address register writeback:
1484 // ...with address register writeback:
[all …]
H A DARMInstrVFP.td134 let Inst{21} = 0; // No writeback
162 let Inst{21} = 0; // No writeback
257 let Inst{21} = 0; // No writeback
H A DARMInstrThumb2.td1714 let Inst{21} = 0; // No writeback
1744 let Inst{21} = 0; // No writeback
1783 let Inst{21} = 0; // No writeback
1819 let Inst{21} = 0; // No writeback
H A DARMInstrInfo.td3053 let Inst{21} = 0; // No writeback
3073 let Inst{21} = 0; // No writeback
3093 let Inst{21} = 0; // No writeback
3113 let Inst{21} = 0; // No writeback
H A DARMInstrThumb.td744 // There is no non-writeback version of STM for Thumb.
H A DARMScheduleSwift.td1128 // Plain load without writeback.
/minix3/external/bsd/llvm/dist/llvm/test/MC/Disassembler/ARM/
H A Dinvalid-thumbv7.txt359 # 32-bit Thumb STM instructions cannot have a writeback register which appears
/minix3/external/bsd/llvm/dist/clang/test/CodeGenObjCXX/
H A Darc.mm281 // a non-dependent message send that requires writeback.
/minix3/external/bsd/llvm/dist/clang/docs/
H A DAutomaticReferenceCounting.rst949 * the conversion is a well-formed :ref:`pass-by-writeback
994 Passing to an out parameter by writeback
999 candidate for :arc-term:`pass-by-writeback`` if:
1005 a pass-by-writeback is always worse than an implicit conversion sequence not
1006 requiring a pass-by-writeback.
1008 The pass-by-writeback is ill-formed if the argument expression does not have a
1025 below, where their store to the writeback temporary is not immediately seen
1028 A pass-by-writeback is evaluated as follows:
1032 and no further work is required for the pass-by-writeback.
1121 caution in the following rules about writeback.