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/minix3/external/bsd/top/dist/machine/
H A Dm_sunos4.man3 a spin lock is displayed along with the other processor state
4 percentages. The percentages shown for processor states are averages
6 processor displayed in the STATE column, for example "run/2" indicates
7 running on processor 2. There is an extra column in the process
8 display indicating which processor each running process is assigned
H A Dm_hpux10.man11 This version of top does not display a per-cpu breakdown of processor
/minix3/external/mit/expat/dist/xmlwf/
H A Dunixfilemap.c22 void (*processor)(const void *, size_t, const char *, void *arg), in filemap()
50 processor(&c, 0, name, arg); in filemap()
61 processor(p, nbytes, name, arg); in filemap()
H A Dfilemap.h9 void (*processor)(const void *, size_t,
14 void (*processor)(const void *, size_t,
H A Dreadfilemap.c45 void (*processor)(const void *, size_t, const char *, void *arg), in filemap()
73 processor(&c, 0, name, arg); in filemap()
96 processor(p, nbytes, name, arg); in filemap()
H A Dwin32filemap.c27 void (*processor)(const void *, size_t, const TCHAR *, void *arg), in filemap()
54 processor(&c, 0, name, arg); in filemap()
71 processor(p, size, name, arg); in filemap()
/minix3/sys/arch/
H A DREADME14 cesfic m68k 20010514 FIC8234 VME processor board
29 i386 i386 19930321 Intel/AMD etc. x86 processor line
30 ia64 ia64 00000000 Intel Itanium/Itanium2 processor based workstations
33 landisk sh3el 20060901 SH4 processor based NAS appliances by I-O DATA
51 sbmips mipseb,mipsel,mips64eb,mips64el 20020306 Broadcom's SiByte processor evaluation boards
78 alpha: Digital Equipment Alpha processor
79 ia64: Intel Itanium/Itanium2 processor
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/AArch64/
H A Dcpus.ll9 ; CHECK-NOT: {{.*}} is not a recognized processor for this target
10 ; INVALID: {{.*}} is not a recognized processor for this target
/minix3/crypto/external/bsd/openssl/dist/doc/crypto/
H A DOPENSSL_ia32cap.pod5 OPENSSL_ia32cap - finding the IA-32 processor capabilities
15 containing IA-32 processor capabilities bit vector as it appears in EDX
38 prior starting target application, e.g. on Intel P4 processor 'env
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSchedule.td28 // processor resources and latency with each SchedReadWrite type.
109 // Define a kind of processor resource that may be common across
113 // Define a number of interchangeable processor resources. NumUnits
162 // SchedModel ties these units to a processor for any stand-alone defs
164 // attached to a processor, so SchedModel is not needed.
178 // Subtargets typically define processor resource kind and number of
232 // SchedModel ties these resources to a processor.
240 // Allow a processor to mark some scheduling classes as unsupported
249 // defined by the subtarget, and maps the SchedWrite to processor
254 // them to processor resources in one place. Then ItinRW can map
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/minix3/external/bsd/llvm/dist/llvm/docs/HistoricalNotes/
H A D2001-04-16-DynamicCompilation.txt32 evolve, and each implementation of an ISA (a processor) must choose a set
34 With every new processor introduced, the vendor faces two fundamental
35 problems: First, there is a lag time between when a processor is introduced
40 processor may be compiled quite sub-optimally for the current
H A D2001-07-06-LoweringIRForCodeGen.txt14 What I was going to suggest was that for a particular processor, we define
16 processor but have VM semantics otherwise, i.e., all operands are in SSA
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/X86/
H A D2008-06-13-VolatileLoadStore.ll11 store volatile double %b, double* @atomic ; one processor operation only
12 store volatile double 0.000000e+00, double* @atomic2 ; one processor operation only
/minix3/external/bsd/file/dist/magic/magdir/
H A Dm45 0 regex \^dnl\ M4 macro processor script text
H A Dalliant6 # If the FX series is the one that had a processor with a 68K-derived
H A Dolf42 >>16 leshort &0xff00 processor-specific,
73 >>16 beshort &0xff00 processor-specific,
H A Dclaris6 # Claris Works a word processor, etc.
/minix3/usr.bin/m4/
H A DNOTES1 m4 - macro processor
6 most of the command set of SysV m4, the standard UN*X macro processor.
/minix3/external/gpl3/binutils/patches/
H A D0009-Slash-means-divide.patch11 pre-processor is disabled, these aren't very useful. The option
/minix3/lib/libc/softfloat/
H A Dsoftfloat-source.txt87 a fixed-point vector processor in collaboration with the University of
134 `<processor>-<executable-type>-<compiler>'. The names of the supplied
137 <processor>:
138 386 - Intel 386-compatible processor.
139 SPARC - SPARC processor (as used by Sun machines).
172 `SPARC-gcc.h'. The naming convention used for processor header files is
173 `<processor>-<compiler>.h'.
276 `milieu.h' header file, which in turn includes the processor header file.
352 The ability of the processor to do fast shifts has been assumed. Efficiency
/minix3/external/bsd/llvm/dist/clang/test/SemaCXX/
H A Dclass-base-member-init.cpp105 void Apply(Foo processor);
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/PowerPC/
H A Dfsl-e500mc.ll5 ; CHECK-NOT: not a recognized processor for this target
H A Dfsl-e5500.ll5 ; CHECK-NOT: not a recognized processor for this target
/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/ARM/
H A Dreadcyclecounter.ll8 ; processor (but not on v6, at least by default).
/minix3/external/mit/expat/dist/lib/
H A Dxmlparse.c611 #define processor (parser->m_processor) macro
842 processor = prologInitProcessor; in parserInit()
1097 processor = externalEntityInitProcessor; in XML_ExternalEntityParserCreate()
1110 processor = externalParEntInitProcessor; in XML_ExternalEntityParserCreate()
1529 errorCode = processor(parser, bufferPtr, parseEndPtr, &bufferPtr); in XML_Parse()
1546 processor = errorProcessor; in XML_Parse()
1558 errorCode = processor(parser, s, parseEndPtr = s + len, &end); in XML_Parse()
1562 processor = errorProcessor; in XML_Parse()
1594 processor = errorProcessor; in XML_Parse()
1651 errorCode = processor(parser, start, parseEndPtr, &bufferPtr); in XML_ParseBuffer()
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