Searched refs:isInsertSubreg (Results 1 – 15 of 15) sorted by relevance
105 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()128 while (UseMI->isCopy() || UseMI->isInsertSubreg()) { in getDefReg()171 } else if (DefMI->isInsertSubreg()) { in hasLoopHazard()
254 if (MI->isInsertSubreg()) { in optimizeSDPattern()337 if (MI->isInsertSubreg() && usesRegClass(MI->getOperand(2), in hasPartialWrite()405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
3631 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() || in getOperandLatency()3921 if (MI->isCopyLike() || MI->isInsertSubreg() || in getPredicationCost()3941 if (MI->isCopyLike() || MI->isInsertSubreg() || in getInstrLatency()
5513 let isInsertSubreg = 1;
67 !MI->isInsertSubreg() && in canTurnIntoImplicitDef()
159 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()671 assert(MI.isInsertSubreg() && "Invalid instruction"); in InsertSubregRewriter()1299 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) && in getNextSourceFromInsertSubreg()1424 if (Def->isInsertSubreg() || Def->isInsertSubregLike()) in getNextSourceImpl()
934 assert((MI.isInsertSubreg() || in getInsertSubregInputs()937 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
453 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence(); in AvoidsSinking()
347 } else if (MI.isInsertSubreg() || MI.isSubregToReg()) { in isCopyToReg()1602 if (mi->isInsertSubreg()) { in runOnMachineFunction()
1656 } else if (TM && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
257 bool isInsertSubreg : 1; variable
510 if (Inst.isInsertSubreg) OS << "|(1<<MCID::InsertSubreg)"; in emitRecord()
322 isInsertSubreg = R->getValueAsBit("isInsertSubreg"); in CodeGenInstruction()
770 bool isInsertSubreg() const {
390 bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?