Home
last modified time | relevance | path

Searched refs:getRegClassFor (Results 1 – 24 of 24) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp98 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
136 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
336 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
337 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
347 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
348 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
500 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
H A DInstrEmitter.cpp108 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
228 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
293 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
456 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
491 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
546 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
H A DFastISel.cpp253 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
742 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1276 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1277 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
1942 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DFunctionLoweringInfo.cpp283 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT)); in CreateReg()
H A DSelectionDAGISel.cpp922 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); in PrepareEHLandingPad()
H A DSelectionDAGBuilder.cpp5335 TLI.getRegClassFor(Src.getSimpleValueType()); in visitIntrinsicCall()
6793 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) in visitInlineAsm()
7761 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()
H A DDAGCombiner.cpp9017 const TargetRegisterClass *ResRC = TLI.getRegClassFor(ResVT.getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
9019 TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT()); in canMergeExpensiveCrossRegisterBankCopy()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMFastISel.cpp450 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
460 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
486 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
502 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
567 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
657 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
671 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
722 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
1029 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
1040 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
[all …]
H A DARMISelLowering.h353 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
H A DARMISelLowering.cpp1152 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const { in getRegClassFor() function in ARMTargetLowering
1162 return TargetLowering::getRegClassFor(VT); in getRegClassFor()
4110 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86FastISel.cpp1703 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
1881 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
1950 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
1978 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2379 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2412 TLI.getRegClassFor(VT), RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
2422 ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg, in fastLowerIntrinsicCall()
2426 TLI.getRegClassFor(VT), LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
2500 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
2583 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerArguments()
[all …]
H A DX86ISelLowering.cpp2537 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
2692 F.VReg = MF.getRegInfo().createVirtualRegister(getRegClassFor(F.VT)); in LowerFormalArguments()
12838 const TargetRegisterClass* rc = getRegClassFor(VecVT); in ExtractBitFromMaskVector()
12988 const TargetRegisterClass* rc = getRegClassFor(VecVT); in InsertBitToMaskVector()
16621 getRegClassFor(getPointerTy()); in LowerDYNAMIC_STACKALLOC()
20551 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); in EmitVAARG64WithCustomInserter()
20552 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); in EmitVAARG64WithCustomInserter()
20991 getRegClassFor(getPointerTy()); in EmitLoweredSegAlloca()
21237 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DCallingConvLower.cpp243 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
H A DMachineScheduler.cpp2395 TLI->getRegClassFor(LegalIntVT)); in initPolicy()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1016 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicBinary()
1117 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1137 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1290 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in emitAtomicCmpSwap()
1373 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
2008 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
2963 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3030 getRegClassFor(Subtarget.isABI_N64() ? MVT::i64 : MVT::i32)); in LowerFormalArguments()
3343 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
3352 RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT); in parseRegForInlineAsmConstraint()
[all …]
H A DMipsSEISelDAGToDAG.cpp882 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in selectNode()
H A DMipsFastISel.cpp891 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp369 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
382 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
402 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
490 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2809 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3036 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3472 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3632 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1373 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1382 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
1855 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in PPCMaterializeFP()
H A DPPCISelLowering.cpp7084 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetLowering.h354 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() function
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp986 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp567 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2500 TLI.getRegClassFor(TLI.getPointerTy())); in LowerRETURNADDR()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIISelLowering.cpp1852 return getRegClassFor(Op.getSimpleValueType()); in getRegClassForNode()