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Searched refs:createVirtualRegister (Results 1 – 25 of 65) sorted by relevance

123

/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp341 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerDynamicAlloc()
365 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
373 NegSizeReg = MF.getRegInfo().createVirtualRegister(G8RC); in lowerDynamicAlloc()
390 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
398 NegSizeReg = MF.getRegInfo().createVirtualRegister(GPRC); in lowerDynamicAlloc()
440 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
452 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRSpilling()
484 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
496 Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRRestore()
557 unsigned Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); in lowerCRBitSpilling()
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H A DPPCISelLowering.cpp6849 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass in EmitAtomicBinary()
6918 unsigned PtrReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6919 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6920 unsigned ShiftReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6921 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6922 unsigned MaskReg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6923 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6924 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6925 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
6926 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC); in EmitPartwordAtomicBinary()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DSIInstrInfo.cpp1355 unsigned Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
1371 unsigned NewSuperReg = MRI.createVirtualRegister(SuperRC); in buildExtractSubReg()
1372 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg()
1419 unsigned LoDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in split64BitImm()
1420 unsigned HiDst = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in split64BitImm()
1421 unsigned Dst = MRI.createVirtualRegister(RC); in split64BitImm()
1608 unsigned DstReg = MRI.createVirtualRegister(RC); in legalizeOperands()
1635 unsigned NewSrc0 = MRI.createVirtualRegister(DstRC); in legalizeOperands()
1671 unsigned Zero64 = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in legalizeOperands()
1672 unsigned SRsrcFormatLo = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass); in legalizeOperands()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXFrameLowering.cpp49 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int64RegsRegClass); in emitPrologue()
58 unsigned LocalReg = MRI.createVirtualRegister(&NVPTX::Int32RegsRegClass); in emitPrologue()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp87 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); in getGlobalBaseReg()
99 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC); in getMips16SPAliasReg()
H A DMipsISelLowering.cpp856 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in addLiveIn()
1047 unsigned StoreVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1048 unsigned AndRes = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1049 unsigned Success = RegInfo.createVirtualRegister(RC); in emitAtomicBinary()
1118 unsigned ScrReg = RegInfo.createVirtualRegister(RC); in emitSignExtendToI32InReg()
1146 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1147 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1148 unsigned Mask = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1149 unsigned Mask2 = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
1150 unsigned NewVal = RegInfo.createVirtualRegister(RC); in emitAtomicBinaryPartword()
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H A DMipsSEFrameLowering.cpp155 unsigned VR = MRI.createVirtualRegister(RC); in expandLoadCCond()
175 unsigned VR = MRI.createVirtualRegister(RC); in expandStoreCCond()
198 unsigned VR0 = MRI.createVirtualRegister(RC); in expandLoadACC()
199 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC()
228 unsigned VR0 = MRI.createVirtualRegister(RC); in expandStoreACC()
229 unsigned VR1 = MRI.createVirtualRegister(RC); in expandStoreACC()
265 unsigned VR0 = MRI.createVirtualRegister(RC); in expandCopyACC()
266 unsigned VR1 = MRI.createVirtualRegister(RC); in expandCopyACC()
H A DMips16ISelDAGToDAG.cpp80 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
81 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
82 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
H A DMipsSEISelLowering.cpp2779 unsigned VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2785 unsigned VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
2847 unsigned RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
2853 unsigned RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
2891 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
2898 unsigned Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
2935 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitCOPY_FD()
2962 unsigned Wt = RegInfo.createVirtualRegister( in emitINSERT_FW()
2999 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); in emitINSERT_FD()
3085 unsigned Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
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H A DMipsSERegisterInfo.cpp172 unsigned Reg = RegInfo.createVirtualRegister(RC); in eliminateFI()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DA15SDOptimizer.cpp431 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane()
451 unsigned Out = MRI->createVirtualRegister(TRC); in createExtractSubreg()
467 unsigned Out = MRI->createVirtualRegister(&ARM::QPRRegClass); in createRegSequence()
486 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createVExt()
502 unsigned Out = MRI->createVirtualRegister(&ARM::DPR_VFP2RegClass); in createInsertSubreg()
518 unsigned Out = MRI->createVirtualRegister(&ARM::DPRRegClass); in createImplicitDef()
H A DARMISelLowering.cpp6549 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6554 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6559 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6576 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6580 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6585 unsigned NewVReg3 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6589 unsigned NewVReg4 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6594 unsigned NewVReg5 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6608 unsigned NewVReg1 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
6613 unsigned NewVReg2 = MRI->createVirtualRegister(TRC); in SetupEntryBlockForSjLj()
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H A DARMInstrInfo.cpp168 MF.getRegInfo().createVirtualRegister(&ARM::rGPRRegClass); in runOnMachineFunction()
H A DThumb1RegisterInfo.cpp116 LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); in emitThumbRegPlusImmInReg()
559 VReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass); in eliminateFrameIndex()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp175 VRBase = MRI->createVirtualRegister(DstRC); in EmitCopyFromReg()
264 VRBase = MRI->createVirtualRegister(RC); in CreateVirtualRegisters()
294 VReg = MRI->createVirtualRegister(RC); in getVR()
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in AddRegisterOperand()
458 unsigned NewReg = MRI->createVirtualRegister(RC); in ConstrainForSubReg()
505 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
519 VRBase = MRI->createVirtualRegister(TRC); in EmitSubregNode()
551 VRBase = MRI->createVirtualRegister(SRC); in EmitSubregNode()
592 unsigned NewVReg = MRI->createVirtualRegister(DstRC); in EmitCopyToRegClassNode()
609 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC)); in EmitRegSequence()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp719 unsigned VReg = MRI.createVirtualRegister(RC); in LowerFormalArguments()
2607 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass); in forceReg()
2765 unsigned OrigVal = MRI.createVirtualRegister(RC); in emitAtomicLoadBinary()
2766 unsigned OldVal = MRI.createVirtualRegister(RC); in emitAtomicLoadBinary()
2768 MRI.createVirtualRegister(RC) : Src2.getReg()); in emitAtomicLoadBinary()
2769 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal); in emitAtomicLoadBinary()
2770 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal); in emitAtomicLoadBinary()
2803 unsigned Tmp = MRI.createVirtualRegister(RC); in emitAtomicLoadBinary()
2813 unsigned Tmp2 = MRI.createVirtualRegister(RC); in emitAtomicLoadBinary()
2884 unsigned OrigVal = MRI.createVirtualRegister(RC); in emitAtomicLoadMinMax()
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H A DSystemZRegisterInfo.cpp101 MF.getRegInfo().createVirtualRegister(&SystemZ::ADDR64BitRegClass); in eliminateFrameIndex()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp328 Src0 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
333 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
340 unsigned Dst = MRI->createVirtualRegister(&AArch64::FPR64RegClass); in transformInstruction()
H A DAArch64CleanupLocalDynamicTLSPass.cpp121 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass); in setRegister()
H A DAArch64RegisterInfo.cpp370 MF.getRegInfo().createVirtualRegister(&AArch64::GPR64RegClass); in eliminateFrameIndex()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp787 unsigned SubR = MRI->createVirtualRegister(IntRC); in computeCount()
813 unsigned AddR = MRI->createVirtualRegister(IntRC); in computeCount()
834 unsigned LsrR = MRI->createVirtualRegister(IntRC); in computeCount()
1085 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in convertToHardwareLoop()
1099 unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in convertToHardwareLoop()
1238 unsigned NewR = MRI->createVirtualRegister(RC); in setImmediate()
1469 unsigned NewPR = MRI->createVirtualRegister(RC); in createPreheaderForLoop()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createEmptyIntervalFrom()
44 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom()
H A DMachineSSAUpdater.cpp119 unsigned NewVR = MRI->createVirtualRegister(RC); in InsertNewDef()
H A DLocalStackSlotAllocation.cpp394 BaseReg = Fn.getRegInfo().createVirtualRegister(RC); in insertFrameReferenceRegisters()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp467 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); in LowerCCCArguments()
1260 unsigned ShiftAmtReg = RI.createVirtualRegister(&MSP430::GR8RegClass); in EmitShiftInstr()
1261 unsigned ShiftAmtReg2 = RI.createVirtualRegister(&MSP430::GR8RegClass); in EmitShiftInstr()
1262 unsigned ShiftReg = RI.createVirtualRegister(RC); in EmitShiftInstr()
1263 unsigned ShiftReg2 = RI.createVirtualRegister(RC); in EmitShiftInstr()

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