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Searched refs:TargetOpcode (Results 1 – 25 of 98) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineInstr.h739 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
740 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
746 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
752 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
761 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
762 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
763 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
764 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
766 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
771 return getOpcode() == TargetOpcode::INSERT_SUBREG;
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/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
211 case TargetOpcode::SUBREG_TO_REG: in runOnMachineFunction()
214 case TargetOpcode::COPY: in runOnMachineFunction()
217 case TargetOpcode::DBG_VALUE: in runOnMachineFunction()
219 case TargetOpcode::INSERT_SUBREG: in runOnMachineFunction()
220 case TargetOpcode::EXTRACT_SUBREG: in runOnMachineFunction()
H A DStackColoring.cpp247 if (MI.getOpcode() != TargetOpcode::LIFETIME_START && in collectMarkers()
248 MI.getOpcode() != TargetOpcode::LIFETIME_END) in collectMarkers()
253 bool IsStart = MI.getOpcode() == TargetOpcode::LIFETIME_START; in collectMarkers()
388 assert((MI->getOpcode() == TargetOpcode::LIFETIME_START || in calculateLiveIntervals()
389 MI->getOpcode() == TargetOpcode::LIFETIME_END) && in calculateLiveIntervals()
392 bool IsStart = MI->getOpcode() == TargetOpcode::LIFETIME_START; in calculateLiveIntervals()
508 if (I.getOpcode() == TargetOpcode::LIFETIME_START || in remapInstructions()
509 I.getOpcode() == TargetOpcode::LIFETIME_END) in remapInstructions()
582 if (I.getOpcode() == TargetOpcode::LIFETIME_START || in removeInvalidSlotRanges()
583 I.getOpcode() == TargetOpcode::LIFETIME_END || I.isDebugValue()) in removeInvalidSlotRanges()
H A DMachineSSAUpdater.cpp151 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
188 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, in GetValueInMiddleOfBlock()
288 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
300 MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc, in CreateEmptyPHI()
H A DPeepholeOptimizer.cpp388 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG) in INITIALIZE_PASS_DEPENDENCY()
445 TII->get(TargetOpcode::COPY), NewVR) in INITIALIZE_PASS_DEPENDENCY()
774 CopyLike.setDesc(TII.get(TargetOpcode::COPY)); in RewriteCurrentSource()
857 case TargetOpcode::COPY: in getCopyRewriter()
859 case TargetOpcode::INSERT_SUBREG: in getCopyRewriter()
861 case TargetOpcode::EXTRACT_SUBREG: in getCopyRewriter()
863 case TargetOpcode::REG_SEQUENCE: in getCopyRewriter()
970 TII->get(TargetOpcode::COPY), in optimizeUncoalescableCopy()
H A DLocalStackSlotAllocation.cpp294 MI->getOpcode() == TargetOpcode::STATEPOINT || in insertFrameReferenceRegisters()
295 MI->getOpcode() == TargetOpcode::STACKMAP || in insertFrameReferenceRegisters()
296 MI->getOpcode() == TargetOpcode::PATCHPOINT) in insertFrameReferenceRegisters()
H A DErlangGC.cpp59 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label); in InsertLabel()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp53 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
54 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
55 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
56 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
57 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
58 case TargetOpcode::COPY: in isResourceAvailable()
59 case TargetOpcode::INLINEASM: in isResourceAvailable()
105 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
106 case TargetOpcode::INSERT_SUBREG: in reserveResources()
107 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
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H A DHexagonNewValueJump.cpp129 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
193 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
194 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
195 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
248 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
H A DHexagonAsmPrinter.cpp185 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE || in EmitInstruction()
186 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) { in EmitInstruction()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), in EmitCopyFromReg()
211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
286 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
339 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); in AddRegisterOperand()
459 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg) in ConstrainForSubReg()
485 if (Opc == TargetOpcode::EXTRACT_SUBREG) { in EmitSubregNode()
507 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg); in EmitSubregNode()
523 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
525 } else if (Opc == TargetOpcode::INSERT_SUBREG || in EmitSubregNode()
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H A DResourcePriorityQueue.cpp263 case TargetOpcode::EXTRACT_SUBREG: in isResourceAvailable()
264 case TargetOpcode::INSERT_SUBREG: in isResourceAvailable()
265 case TargetOpcode::SUBREG_TO_REG: in isResourceAvailable()
266 case TargetOpcode::REG_SEQUENCE: in isResourceAvailable()
267 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
303 case TargetOpcode::EXTRACT_SUBREG: in reserveResources()
304 case TargetOpcode::INSERT_SUBREG: in reserveResources()
305 case TargetOpcode::SUBREG_TO_REG: in reserveResources()
306 case TargetOpcode::REG_SEQUENCE: in reserveResources()
307 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
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H A DFastISel.cpp255 TII.get(TargetOpcode::IMPLICIT_DEF), Reg); in materializeConstant()
346 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL) in recomputeInsertPt()
653 TII.get(TargetOpcode::STACKMAP)); in selectStackmap()
820 TII.get(TargetOpcode::PATCHPOINT)); in selectPatchpoint()
1045 TII.get(TargetOpcode::INLINEASM)) in selectCall()
1128 TII.get(TargetOpcode::DBG_VALUE), false, Op->getReg(), 0, in selectIntrinsicCall()
1132 TII.get(TargetOpcode::DBG_VALUE)) in selectIntrinsicCall()
1147 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in selectIntrinsicCall()
1282 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0); in selectBitCast()
1692 TII.get(TargetOpcode::COPY), NewOp).addReg(Op); in constrainOperandRegClass()
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H A DScheduleDAGRRList.cpp298 if (Opcode == TargetOpcode::REG_SEQUENCE) { in GetCostForDef()
1898 if (Opc == TargetOpcode::EXTRACT_SUBREG || in getNodePriority()
1899 Opc == TargetOpcode::SUBREG_TO_REG || in getNodePriority()
1900 Opc == TargetOpcode::INSERT_SUBREG) in getNodePriority()
2118 if (Opc == TargetOpcode::EXTRACT_SUBREG || in unscheduledNode()
2119 Opc == TargetOpcode::INSERT_SUBREG || in unscheduledNode()
2120 Opc == TargetOpcode::SUBREG_TO_REG || in unscheduledNode()
2121 Opc == TargetOpcode::REG_SEQUENCE || in unscheduledNode()
2122 Opc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
2145 if (POpc == TargetOpcode::IMPLICIT_DEF) in unscheduledNode()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp302 case TargetOpcode::CFI_INSTRUCTION: in GetInstSizeInBytes()
303 case TargetOpcode::EH_LABEL: in GetInstSizeInBytes()
304 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()
305 case TargetOpcode::KILL: in GetInstSizeInBytes()
306 case TargetOpcode::DBG_VALUE: in GetInstSizeInBytes()
308 case TargetOpcode::INLINEASM: { in GetInstSizeInBytes()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp131 case TargetOpcode::COPY: in expandInstr()
159 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
204 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY); in expandLoadACC()
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
445 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
476 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
481 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
492 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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H A DMips16FrameLowering.cpp57 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
72 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CleanupLocalDynamicTLSPass.cpp102 TII->get(TargetOpcode::COPY), in replaceTLSBaseAddrCall()
126 TII->get(TargetOpcode::COPY), in setRegister()
H A DAArch64FrameLowering.cpp198 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitCalleeSavedFrameMoves()
242 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
386 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
394 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
401 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
408 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
H A DAArch64AsmPrinter.cpp395 MII->getOpcode() == TargetOpcode::PATCHPOINT || in LowerSTACKMAP()
396 MII->getOpcode() == TargetOpcode::STACKMAP) in LowerSTACKMAP()
554 case TargetOpcode::STACKMAP: in EmitInstruction()
557 case TargetOpcode::PATCHPOINT: in EmitInstruction()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetOpcodes.h24 namespace TargetOpcode {
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DThumb1FrameLowering.cpp126 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
138 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
203 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
231 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
250 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
257 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
275 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.cpp560 BuildMI(MBB, II, dl, TII.get(TargetOpcode::KILL), in lowerCRBitSpilling()
608 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg); in lowerCRBitRestore()
728 else if (MI.getOpcode() == TargetOpcode::STACKMAP || in getOffsetONFromFION()
729 MI.getOpcode() == TargetOpcode::PATCHPOINT) in getOffsetONFromFION()
802 bool noImmForm = !MI.isInlineAsm() && OpC != TargetOpcode::STACKMAP && in eliminateFrameIndex()
803 OpC != TargetOpcode::PATCHPOINT && !ImmToIdxMap.count(OpC); in eliminateFrameIndex()
829 OpC == TargetOpcode::STACKMAP || in eliminateFrameIndex()
830 OpC == TargetOpcode::PATCHPOINT)) { in eliminateFrameIndex()
860 else if (OpC != TargetOpcode::INLINEASM) { in eliminateFrameIndex()
1041 MI->getOpcode() == TargetOpcode::STACKMAP || in isFrameOffsetLegal()
[all …]
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp118 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
123 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
131 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp342 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
357 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
371 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
404 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()

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