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Searched refs:SequentiallyConsistent (Results 1 – 22 of 22) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/test/CodeGen/CPP/
H A Datomic.ll5 …[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Xchg, {{.*}}, SequentiallyConsistent, CrossThre…
10 …:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Add, {{.*}}, SequentiallyConsistent, CrossThre…
30 …T:[a-zA-Z0-9_]+]] = new AtomicRMWInst(AtomicRMWInst::Or, {{.*}}, SequentiallyConsistent, SingleThr…
65 …XchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic…
77 …XchgInst* [[INST:[a-zA-Z0-9_]+]] = new AtomicCmpXchgInst({{.*}}, SequentiallyConsistent, Monotonic…
/minix3/external/bsd/llvm/dist/llvm/docs/
H A DAtomics.rst37 stated order. A couple examples: if a SequentiallyConsistent store is
38 immediately followed by another SequentiallyConsistent store to the same
119 equivalent to a Release store. SequentiallyConsistent fences behave as both
328 SequentiallyConsistent section in Atomic orderings
331 SequentiallyConsistent (``seq_cst`` in IR) provides Acquire semantics for loads
333 ordering exists between all SequentiallyConsistent operations.
346 SequentiallyConsistent loads and stores, the same reorderings are allowed as
347 for Acquire loads and Release stores, except that SequentiallyConsistent
351 SequentiallyConsistent loads minimally require the same barriers as Acquire
352 operations and SequentiallyConsistent stores require Release
[all …]
/minix3/external/bsd/llvm/dist/clang/lib/CodeGen/
H A DCGAtomic.cpp256 FailureOrder = llvm::SequentiallyConsistent; in emitAtomicCmpXchgFailureSet()
275 if (SuccessOrder == llvm::SequentiallyConsistent) in emitAtomicCmpXchgFailureSet()
305 Size, Align, SuccessOrder, llvm::SequentiallyConsistent); in emitAtomicCmpXchgFailureSet()
814 Size, Align, llvm::SequentiallyConsistent); in EmitAtomicExpr()
882 Size, Align, llvm::SequentiallyConsistent); in EmitAtomicExpr()
992 load->setAtomic(llvm::SequentiallyConsistent); in EmitAtomicLoad()
1133 if (!isInit) store->setAtomic(llvm::SequentiallyConsistent); in EmitAtomicStore()
H A DCGBuiltin.cpp107 llvm::SequentiallyConsistent); in EmitBinaryAtomic()
142 llvm::SequentiallyConsistent); in EmitBinaryAtomicPost()
1022 llvm::SequentiallyConsistent, in EmitBuiltinExpr()
1023 llvm::SequentiallyConsistent); in EmitBuiltinExpr()
1049 llvm::SequentiallyConsistent, in EmitBuiltinExpr()
1050 llvm::SequentiallyConsistent); in EmitBuiltinExpr()
1097 Builder.CreateFence(llvm::SequentiallyConsistent); in EmitBuiltinExpr()
1166 llvm::SequentiallyConsistent); in EmitBuiltinExpr()
1184 llvm::AcquireRelease, llvm::SequentiallyConsistent in EmitBuiltinExpr()
1236 Store->setOrdering(llvm::SequentiallyConsistent); in EmitBuiltinExpr()
[all …]
H A DCGExprScalar.cpp1617 llvm::SequentiallyConsistent)); in EmitScalarPrePostIncDec()
1623 LV.getAddress(), True, llvm::SequentiallyConsistent); in EmitScalarPrePostIncDec()
1640 LV.getAddress(), amt, llvm::SequentiallyConsistent); in EmitScalarPrePostIncDec()
2109 llvm::SequentiallyConsistent); in EmitCompoundAssignLValue()
H A DCodeGenFunction.h2095 llvm::AtomicOrdering Success = llvm::SequentiallyConsistent,
2096 llvm::AtomicOrdering Failure = llvm::SequentiallyConsistent,
/minix3/external/bsd/llvm/dist/llvm/include/llvm/IR/
H A DInstructions.h45 SequentiallyConsistent = 7 enumerator
58 Ord == SequentiallyConsistent); in isAtLeastAcquire()
66 Ord == SequentiallyConsistent); in isAtLeastRelease()
601 case SequentiallyConsistent:
602 return SequentiallyConsistent;
/minix3/external/bsd/llvm/dist/llvm/lib/Transforms/Instrumentation/
H A DThreadSanitizer.cpp432 case SequentiallyConsistent: v = 5; break; in createOrdering()
H A DMemorySanitizer.cpp1086 case SequentiallyConsistent: in addReleaseOrdering()
1087 return SequentiallyConsistent; in addReleaseOrdering()
1103 case SequentiallyConsistent: in addAcquireOrdering()
1104 return SequentiallyConsistent; in addAcquireOrdering()
/minix3/external/bsd/llvm/dist/llvm/lib/IR/
H A DAsmWriter.cpp1501 case SequentiallyConsistent: Out << " seq_cst"; break; in writeAtomic()
1522 case SequentiallyConsistent: Out << " seq_cst"; break; in writeAtomicCmpXchg()
1532 case SequentiallyConsistent: Out << " seq_cst"; break; in writeAtomicCmpXchg()
H A DVerifier.cpp2114 Ordering == AcquireRelease || Ordering == SequentiallyConsistent, in visitFenceInst()
H A DCore.cpp2491 return SequentiallyConsistent; in mapFromLLVMOrdering()
/minix3/external/bsd/llvm/dist/llvm/bindings/ocaml/llvm/
H A Dllvm.ml242 | SequentiallyConsistent Constructor
H A Dllvm.mli307 | SequentiallyConsistent Constructor
/minix3/external/bsd/llvm/dist/llvm/lib/Target/CppBackend/
H A DCPPBackend.cpp1098 case SequentiallyConsistent: return "SequentiallyConsistent"; in ConvertAtomicOrdering()
/minix3/external/bsd/llvm/dist/llvm/lib/Bitcode/Writer/
H A DBitcodeWriter.cpp129 case SequentiallyConsistent: return bitc::ORDERING_SEQCST; in GetEncodedOrdering()
/minix3/external/bsd/llvm/dist/llvm/test/Bindings/Ocaml/
H A Dcore.ml1395 AtomicOrdering.SequentiallyConsistent false "build_atomicrmw"
/minix3/external/bsd/llvm/dist/llvm/lib/Bitcode/Reader/
H A DBitcodeReader.cpp295 case bitc::ORDERING_SEQCST: return SequentiallyConsistent; in GetDecodedOrdering()
/minix3/external/bsd/llvm/dist/llvm/lib/AsmParser/
H A DLLParser.cpp1599 case lltok::kw_seq_cst: Ordering = SequentiallyConsistent; break; in ParseOrdering()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp11062 case SequentiallyConsistent: in emitLeadingFence()
11092 case SequentiallyConsistent: in emitTrailingFence()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp6800 if (Ord == SequentiallyConsistent) in emitLeadingFence()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19248 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { in LowerATOMIC_FENCE()
19522 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || in LowerATOMIC_STORE()