Searched refs:RegisterMask (Results 1 – 7 of 7) sorted by relevance
| /minix3/external/bsd/llvm/dist/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.cpp | 148 void Decoder::printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask) { in printRegisters() argument
154 const uint16_t GPRMask = std::get<0>(RegisterMask); in printRegisters()
155 const uint16_t VFPMask = std::get<1>(RegisterMask); in printRegisters()
245 uint16_t RegisterMask = (Link << (Prologue ? 14 : 15)) in opcode_10Lxxxxx() local
248 assert((~RegisterMask & (1 << 13)) && "sp must not be set"); in opcode_10Lxxxxx()
249 assert((~RegisterMask & (1 << (Prologue ? 15 : 14))) && "pc must not be set"); in opcode_10Lxxxxx()
254 printRegisters(std::make_pair(RegisterMask, 0)); in opcode_10Lxxxxx()
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| H A D | ARMWinEHPrinter.h | 81 void printRegisters(const std::pair<uint16_t, uint32_t> &RegisterMask);
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| /minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, enumerator
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| H A D | SelectionDAGNodes.h | 1715 : SDNode(ISD::RegisterMask, 0, DebugLoc(), getSDVTList(MVT::Untyped)),
1722 return N->getOpcode() == ISD::RegisterMask;
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| /minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 85 case ISD::RegisterMask: return "RegisterMask"; in getOperationName()
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| H A D | SelectionDAGISel.cpp | 2500 case ISD::RegisterMask: in SelectCodeCommon()
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| H A D | SelectionDAG.cpp | 445 case ISD::RegisterMask: in AddNodeIDCustom()
1642 AddNodeIDNode(ID, ISD::RegisterMask, getVTList(MVT::Untyped), None); in getRegisterMask()
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