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Searched refs:OutputArg (Results 1 – 25 of 40) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsCCState.h38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
73 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
87 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
110 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
118 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, in CheckReturn()
H A DMipsCCState.cpp93 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForF128()
106 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands()
H A DMipsISelLowering.h466 const SmallVectorImpl<ISD::OutputArg> &Outs,
471 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetCallingConv.h167 struct OutputArg { struct
183 OutputArg() : IsFixed(false) {} in OutputArg() function
184 OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed, in OutputArg() argument
H A DTargetLowering.h2315 SmallVector<ISD::OutputArg, 32> Outs;
2440 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, in CanLowerReturn() argument
2453 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/, in LowerReturn() argument
2820 SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h139 const SmallVectorImpl<ISD::OutputArg> &Outs,
206 const SmallVectorImpl<ISD::OutputArg> &Outs,
213 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
H A DXCoreISelLowering.cpp1045 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
1122 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerCCCCallTo()
1452 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
1466 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h123 const SmallVectorImpl<ISD::OutputArg> &Outs,
128 const SmallVectorImpl<ISD::OutputArg> &Outs,
133 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DSparcISelLowering.cpp173 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
184 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_32()
246 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn_64()
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall_32()
1007 ArrayRef<ISD::OutputArg> Outs) { in fixupVariableFloatArgs()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h83 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
88 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonCallingConvLower.cpp96 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
133 Hexagon_CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> in AnalyzeCallOperands()
H A DHexagonISelLowering.h97 SmallVectorImpl<ISD::OutputArg> &Outs,
140 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DHexagonISelLowering.cpp317 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
399 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
1672 const SmallVectorImpl<ISD::OutputArg> &Outs, in IsEligibleForTailCallOptimization()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DCallingConvLower.cpp88 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn()
102 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
120 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h129 const SmallVectorImpl<ISD::OutputArg> &Outs,
161 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DMSP430ISelLowering.cpp269 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeVarArgs()
354 const SmallVectorImpl<ISD::OutputArg> &Outs) { in AnalyzeRetResult()
398 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
526 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
580 const SmallVectorImpl<ISD::OutputArg> in LowerCCCCallTo()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h286 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
292 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
297 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h710 const SmallVectorImpl<ISD::OutputArg> &Outs,
716 const SmallVectorImpl<ISD::OutputArg> &Outs,
752 const SmallVectorImpl<ISD::OutputArg> &Outs,
761 const SmallVectorImpl<ISD::OutputArg> &Outs,
769 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h371 const SmallVectorImpl<ISD::OutputArg> &Outs,
390 const SmallVectorImpl<ISD::OutputArg> &Outs,
394 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.h563 const SmallVectorImpl<ISD::OutputArg> &Outs,
570 const SmallVectorImpl<ISD::OutputArg> &Outs,
576 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h484 const SmallVectorImpl<ISD::OutputArg> &,
490 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.h892 const SmallVectorImpl<ISD::OutputArg> &Outs,
964 const SmallVectorImpl<ISD::OutputArg> &Outs,
977 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h244 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.h137 const SmallVectorImpl<ISD::OutputArg> &Outs,
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DFunctionLoweringInfo.cpp89 SmallVector<ISD::OutputArg, 4> Outs; in set()

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