| /minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 274 for (unsigned IntVT = MVT::FIRST_INTEGER_VALUETYPE; in getHalfSizedIntegerVT() local
275 IntVT <= MVT::LAST_INTEGER_VALUETYPE; ++IntVT) { in getHalfSizedIntegerVT()
276 EVT HalfVT = EVT((MVT::SimpleValueType)IntVT); in getHalfSizedIntegerVT()
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| /minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FunctionLoweringInfo.cpp | 347 EVT IntVT = ValueVTs[0]; in ComputePHILiveOutRegInfo() local
349 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) in ComputePHILiveOutRegInfo()
351 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); in ComputePHILiveOutRegInfo()
352 unsigned BitWidth = IntVT.getSizeInBits(); in ComputePHILiveOutRegInfo()
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| H A D | TargetLowering.cpp | 2914 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), in expandFP_TO_SINT() local
2916 SDValue ExponentMask = DAG.getConstant(0x7F800000, IntVT); in expandFP_TO_SINT()
2917 SDValue ExponentLoBit = DAG.getConstant(23, IntVT); in expandFP_TO_SINT()
2918 SDValue Bias = DAG.getConstant(127, IntVT); in expandFP_TO_SINT()
2920 IntVT); in expandFP_TO_SINT()
2921 SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, IntVT); in expandFP_TO_SINT()
2922 SDValue MantissaMask = DAG.getConstant(0x007FFFFF, IntVT); in expandFP_TO_SINT()
2924 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, IntVT, Node->getOperand(0)); in expandFP_TO_SINT()
2926 SDValue ExponentBits = DAG.getNode(ISD::SRL, dl, IntVT, in expandFP_TO_SINT()
2927 DAG.getNode(ISD::AND, dl, IntVT, Bits, ExponentMask), in expandFP_TO_SINT()
[all …]
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| H A D | FastISel.cpp | 229 EVT IntVT = TLI.getPointerTy(); in materializeConstant() local
232 uint32_t IntBitWidth = IntVT.getSizeInBits(); in materializeConstant()
242 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg, in materializeConstant()
1396 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits()); in selectFNeg() local
1397 if (!TLI.isTypeLegal(IntVT)) in selectFNeg()
1400 unsigned IntReg = fastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(), in selectFNeg()
1406 IntVT.getSimpleVT(), ISD::XOR, IntReg, /*IsKill=*/true, in selectFNeg()
1407 UINT64_C(1) << (VT.getSizeInBits() - 1), IntVT.getSimpleVT()); in selectFNeg()
1411 ResultReg = fastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(), ISD::BITCAST, in selectFNeg()
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| H A D | DAGCombiner.cpp | 6715 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); in ConstantFoldBITCASTofBUILD_VECTOR() local
6716 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); in ConstantFoldBITCASTofBUILD_VECTOR()
6717 SrcEltVT = IntVT; in ConstantFoldBITCASTofBUILD_VECTOR()
7884 EVT IntVT = Int.getValueType(); in visitFNEG() local
7885 if (IntVT.isInteger() && !IntVT.isVector()) { in visitFNEG()
7891 SignMask = APInt::getSplat(IntVT.getSizeInBits(), SignMask); in visitFNEG()
7894 SignMask = APInt::getSignBit(IntVT.getSizeInBits()); in visitFNEG()
7896 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int, in visitFNEG()
7897 DAG.getConstant(SignMask, IntVT)); in visitFNEG()
7991 EVT IntVT = Int.getValueType(); in visitFABS() local
[all …]
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| H A D | SelectionDAGBuilder.cpp | 183 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyFromParts() local
184 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT, V); in getCopyFromParts()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/ |
| H A D | AMDGPUISelLowering.cpp | 1533 MVT IntVT = MVT::i32; in LowerDIVREM24() local
1541 IntVT = MVT::getVectorVT(MVT::i32, NElts); in LowerDIVREM24()
1547 SDValue jq = DAG.getConstant(1, IntVT); in LowerDIVREM24()
1560 jq = DAG.getSExtOrTrunc(jq, DL, IntVT); in LowerDIVREM24()
1565 DAG.getSExtOrTrunc(LHS, DL, IntVT) : DAG.getZExtOrTrunc(LHS, DL, IntVT); in LowerDIVREM24()
1569 DAG.getSExtOrTrunc(RHS, DL, IntVT) : DAG.getZExtOrTrunc(RHS, DL, IntVT); in LowerDIVREM24()
1592 SDValue iq = DAG.getNode(ToInt, DL, IntVT, fq); in LowerDIVREM24()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2672 MVT IntVT = Is64Bit ? MVT::i64 : MVT::i32; in LowerFormalArguments() local
2673 RegParmTypes.push_back(IntVT); in LowerFormalArguments()
24254 MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32; in CMPEQCombine() local
24268 IntVT = MVT::i32; in CMPEQCombine()
24271 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF); in CMPEQCombine()
24272 SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI, in CMPEQCombine()
24273 DAG.getConstant(1, IntVT)); in CMPEQCombine()
25727 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
25732 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
25733 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
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| /minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 6923 EVT IntVT = BV->getValueType(0); in performVectorCompareAndMaskUnaryOpCombine() local
6928 SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst); in performVectorCompareAndMaskUnaryOpCombine()
6929 SDValue NewAnd = DAG.getNode(ISD::AND, DL, IntVT, in performVectorCompareAndMaskUnaryOpCombine()
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