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Searched refs:ExtType (Results 1 – 20 of 20) sorted by relevance

/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetLowering.h565 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const { in getLoadExtAction() argument
569 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE && in getLoadExtAction()
571 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType]; in getLoadExtAction()
575 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const { in isLoadExtLegal() argument
577 getLoadExtAction(ExtType, ValVT, MemVT) == Legal; in isLoadExtLegal()
1250 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT, in setLoadExtAction() argument
1252 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() && in setLoadExtAction()
1254 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action; in setLoadExtAction()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1000 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); in printArithExtend() local
1006 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1010 ExtType == AArch64_AM::UXTX) || in printArithExtend()
1012 ExtType == AArch64_AM::UXTW) ) { in printArithExtend()
1018 O << ", " << AArch64_AM::getShiftExtendName(ExtType); in printArithExtend()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp201 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp() local
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) in LegalizeOp()
479 ISD::LoadExtType ExtType = LD->getExtensionType(); in ExpandLoad() local
571 switch (ExtType) { in ExpandLoad()
593 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, in ExpandLoad()
H A DLegalizeVectorTypes.cpp949 ISD::LoadExtType ExtType = LD->getExtensionType(); in SplitVecRes_LOAD() local
963 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
970 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
995 ISD::LoadExtType ExtType = MLD->getExtensionType(); in SplitVecRes_MLOAD() local
1020 ExtType); in SplitVecRes_MLOAD()
1032 ExtType); in SplitVecRes_MLOAD()
2389 ISD::LoadExtType ExtType = LD->getExtensionType(); in WidenVecRes_LOAD() local
2393 if (ExtType != ISD::NON_EXTLOAD) in WidenVecRes_LOAD()
2394 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType); in WidenVecRes_LOAD()
2420 ISD::LoadExtType ExtType = N->getExtensionType(); in WidenVecRes_MLOAD() local
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H A DLegalizeDAG.cpp875 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeLoadOps() local
876 if (ExtType == ISD::NON_EXTLOAD) { in LegalizeLoadOps()
947 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) == in LegalizeLoadOps()
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; in LegalizeLoadOps()
969 if (ExtType == ISD::SEXTLOAD) in LegalizeLoadOps()
974 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) in LegalizeLoadOps()
1008 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1029 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, in LegalizeLoadOps()
1060 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0), in LegalizeLoadOps()
1098 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) { in LegalizeLoadOps()
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H A DLegalizeIntegerTypes.cpp446 ISD::LoadExtType ExtType = in PromoteIntRes_LOAD() local
449 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
1958 ISD::LoadExtType ExtType = N->getExtensionType(); in ExpandIntRes_LOAD() local
1971 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
1978 if (ExtType == ISD::SEXTLOAD) { in ExpandIntRes_LOAD()
1984 } else if (ExtType == ISD::ZEXTLOAD) { in ExpandIntRes_LOAD()
1988 assert(ExtType == ISD::EXTLOAD && "Unknown extload!"); in ExpandIntRes_LOAD()
2006 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, in ExpandIntRes_LOAD()
2024 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(), in ExpandIntRes_LOAD()
2052 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, in ExpandIntRes_LOAD()
H A DSelectionDAG.cpp237 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { in getExtForLoadExtType() argument
238 switch (ExtType) { in getExtForLoadExtType()
2531 unsigned ExtType = LD->getExtensionType(); in ComputeNumSignBits() local
2532 switch (ExtType) { in ComputeNumSignBits()
4640 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4669 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO); in getLoad()
4673 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, in getLoad() argument
4678 ExtType = ISD::NON_EXTLOAD; in getLoad()
4679 } else if (ExtType == ISD::NON_EXTLOAD) { in getLoad()
4704 ID.AddInteger(encodeMemSDNodeFlags(ExtType, AM, MMO->isVolatile(), in getLoad()
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H A DDAGCombiner.cpp213 ISD::NodeType ExtType);
877 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteOperand() local
882 return DAG.getExtLoad(ExtType, dl, PVT, in PromoteOperand()
1099 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) in PromoteLoad() local
1103 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, in PromoteLoad()
5255 ISD::NodeType ExtType) { in ExtendSetCCUses() argument
5266 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); in ExtendSetCCUses()
5891 ISD::LoadExtType ExtType = LN0->getExtensionType(); in visitANY_EXTEND() local
5893 if (!LegalOperations || TLI.isLoadExtLegal(ExtType, VT, MemVT)) { in visitANY_EXTEND()
5894 SDValue ExtLoad = DAG.getExtLoad(ExtType, SDLoc(N), in visitANY_EXTEND()
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H A DLegalizeTypes.h684 LoadSDNode *LD, ISD::LoadExtType ExtType);
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.h128 ISD::LoadExtType ExtType,
H A DAMDGPUISelLowering.cpp1404 ISD::LoadExtType ExtType = Load->getExtensionType(); in LowerLOAD() local
1408 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) { in LowerLOAD()
1430 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32)) in LowerLOAD()
1449 if (ExtType == ISD::SEXTLOAD) { in LowerLOAD()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h829 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
834 SDValue getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT,
839 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
846 SDValue getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp2140 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; in LowerFormalArguments() local
2150 ExtType = ISD::SEXTLOAD; in LowerFormalArguments()
2153 ExtType = ISD::ZEXTLOAD; in LowerFormalArguments()
2156 ExtType = ISD::EXTLOAD; in LowerFormalArguments()
2160 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN, in LowerFormalArguments()
7491 unsigned ExtType = LHS.getOpcode(); in performAddSubLongCombine() local
7500 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS); in performAddSubLongCombine()
7506 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS); in performAddSubLongCombine()
8111 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { in checkValueWidth() argument
8112 ExtType = ISD::NON_EXTLOAD; in checkValueWidth()
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H A DAArch64FastISel.cpp54 AArch64_AM::ShiftExtendType ExtType; member in __anon23467fb50111::AArch64FastISel::Address
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend), in Address()
69 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; } in setExtendType()
70 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; } in getExtendType()
174 AArch64_AM::ShiftExtendType ExtType,
1349 AArch64_AM::ShiftExtendType ExtType, in emitAddSub_rx() argument
1382 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
H A DAArch64ISelDAGToDAG.cpp974 ISD::LoadExtType ExtType = LD->getExtensionType(); in SelectIndexedLoad() local
979 if (ExtType == ISD::NON_EXTLOAD) in SelectIndexedLoad()
981 else if (ExtType == ISD::SEXTLOAD) in SelectIndexedLoad()
991 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
1004 if (ExtType == ISD::SEXTLOAD) { in SelectIndexedLoad()
H A DAArch64InstrInfo.cpp1285 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); in isScaledAddr() local
1286 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.td848 ISD::LoadExtType ExtType = LD->getExtensionType();
849 if (ExtType == ISD::NON_EXTLOAD)
851 if (ExtType == ISD::EXTLOAD)
858 ISD::LoadExtType ExtType = LD->getExtensionType();
859 if (ExtType == ISD::EXTLOAD)
866 ISD::LoadExtType ExtType = LD->getExtensionType();
867 if (ExtType == ISD::NON_EXTLOAD)
869 if (ExtType == ISD::EXTLOAD)
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2154 ISD::LoadExtType ExtType = LD->getExtensionType(); in lowerLOAD() local
2164 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) { in lowerLOAD()
2183 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) || in lowerLOAD()
2184 (ExtType == ISD::EXTLOAD)) in lowerLOAD()
2187 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD)); in lowerLOAD()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1186 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ? in adjustSubwordCmp() local
1190 Load->getExtensionType() != ExtType) in adjustSubwordCmp()
1191 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32, in adjustSubwordCmp()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp3993 unsigned ExtType = in PerformANDCombine() local
3996 if (ExtType == ISD::SEXTLOAD) { in PerformANDCombine()