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Searched refs:Defs (Results 1 – 25 of 81) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp46 SmallSet<unsigned, 4> &Defs,
57 SmallSet<unsigned, 4> &Defs, in TrackDefUses() argument
87 Defs.insert(*Subreg); in TrackDefUses()
108 SmallSet<unsigned, 4> &Defs, in MoveCopyOutOfITBlock() argument
123 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
165 SmallSet<unsigned, 4> Defs; in InsertITInstructions() local
178 Defs.clear(); in InsertITInstructions()
180 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
221 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
230 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
H A DA15SDOptimizer.cpp409 SmallVector<unsigned, 8> Defs; in getReadDPRs() local
420 Defs.push_back(MO.getReg()); in getReadDPRs()
422 return Defs; in getReadDPRs()
616 SmallVector<unsigned, 8> Defs = getReadDPRs(MI); in runOnInstruction() local
619 for (SmallVectorImpl<unsigned>::iterator I = Defs.begin(), E = Defs.end(); in runOnInstruction()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td90 class Defs<list<Register> Regs> {
91 list<Register> Defs = Regs;
518 Defs<[DSPOutFlag20]>;
522 IsCommutable, Defs<[DSPOutFlag20]>;
526 Defs<[DSPOutFlag20]>;
530 Defs<[DSPOutFlag20]>;
534 Defs<[DSPOutFlag20]>;
538 IsCommutable, Defs<[DSPOutFlag20]>;
542 Defs<[DSPOutFlag20]>;
546 Defs<[DSPOutFlag20]>;
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H A DMipsDelaySlotFiller.cpp96 BitVector Defs, Uses; member in __anone034af290111::RegDefsUses
160 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anone034af290111::MemDefsUses
297 Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {} in RegDefsUses()
306 Defs.set(Mips::RA); in init()
312 Defs.reset(Mips::AT); in init()
329 Defs |= CallerSavedRegs; in setCallerSaved()
342 Defs |= AllocSet.flip(); in setUnallocatableRegs()
366 Defs |= NewDefs; in update()
377 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg)); in checkRegDefsUses()
382 return isRegInSet(Defs, Reg); in checkRegDefsUses()
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H A DMips32r6InstrInfo.td304 list<Register> Defs = [AT];
312 list<Register> Defs = [AT];
320 list<Register> Defs = [AT];
326 list<Register> Defs = [RA];
331 list<Register> Defs = [RA];
387 list<Register> Defs = [RA];
392 list<Register> Defs = [AT];
430 list<Register> Defs = [RA];
434 list<Register> Defs = [RA];
438 list<Register> Defs = [RA];
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H A DMips16InstrInfo.td562 let Defs = [SP];
569 let Defs = [SP];
699 let Defs = [T8];
708 let Defs = [T8];
717 let Defs = [T8];
727 let Defs = [HI0, LO0];
736 let Defs = [HI0, LO0];
748 let Defs = [RA];
754 let Defs = [RA];
901 let Defs = [HI0, LO0];
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/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DLivePhysRegs.cpp66 SmallVector<unsigned, 4> Defs; in stepForward() local
75 Defs.push_back(Reg); in stepForward()
87 for (unsigned i = 0, e = Defs.size(); i != e; ++i) in stepForward()
88 addReg(Defs[i]); in stepForward()
H A DLiveVariables.cpp443 SmallVectorImpl<unsigned> &Defs) { in HandlePhysRegDef() argument
482 Defs.push_back(Reg); // Remember this def. in HandlePhysRegDef()
486 SmallVectorImpl<unsigned> &Defs) { in UpdatePhysRegDefs() argument
487 while (!Defs.empty()) { in UpdatePhysRegDefs()
488 unsigned Reg = Defs.back(); in UpdatePhysRegDefs()
489 Defs.pop_back(); in UpdatePhysRegDefs()
500 SmallVectorImpl<unsigned> &Defs) { in runOnInstr() argument
553 HandlePhysRegDef(MOReg, MI, Defs); in runOnInstr()
555 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
560 SmallVector<unsigned, 4> Defs; in runOnBlock() local
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H A DMachineCopyPropagation.cpp73 const DestList& Defs = SI->second; in SourceNoLongerAvailable() local
74 for (DestList::const_iterator I = Defs.begin(), E = Defs.end(); in SourceNoLongerAvailable()
239 SmallVector<unsigned, 2> Defs; in CopyPropagateBlock() local
256 Defs.push_back(Reg); in CopyPropagateBlock()
299 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in CopyPropagateBlock()
300 unsigned Reg = Defs[i]; in CopyPropagateBlock()
H A DMachineInstrBundle.cpp123 SmallVector<MachineOperand*, 4> Defs; in finalizeBundle() local
130 Defs.push_back(&MO); in finalizeBundle()
155 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in finalizeBundle()
156 MachineOperand &MO = *Defs[i]; in finalizeBundle()
183 Defs.clear(); in finalizeBundle()
H A DRegisterPressure.cpp318 SmallVector<unsigned, 8> Defs; member in RegisterOperands
337 pushRegUnits(MO.getReg(), Defs); in collect()
367 std::bind1st(std::ptr_fun(containsReg), RegOpers.Defs)); in collectOperands()
414 for (unsigned i = 0, e = RegOpers.Defs.size(); i != e; ++i) in collectPDiff()
415 PDiff.addPressureChange(RegOpers.Defs[i], true, MRI); in collectPDiff()
499 for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) { in recede()
500 unsigned Reg = RegOpers.Defs[i]; in recede()
543 for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) { in recede()
544 unsigned Reg = RegOpers.Defs[i]; in recede()
604 for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) { in advance()
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H A DMachineLICM.cpp849 SmallVector<unsigned, 4> Defs; in UpdateRegPressure() local
860 Defs.push_back(Reg); in UpdateRegPressure()
872 while (!Defs.empty()) { in UpdateRegPressure()
873 unsigned Reg = Defs.pop_back_val(); in UpdateRegPressure()
1330 SmallVector<unsigned, 2> Defs; in EliminateCSE() local
1342 Defs.push_back(i); in EliminateCSE()
1346 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in EliminateCSE()
1347 unsigned Idx = Defs[i]; in EliminateCSE()
1355 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
1360 for (unsigned i = 0, e = Defs.size(); i != e; ++i) { in EliminateCSE()
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/minix3/external/bsd/llvm/dist/llvm/utils/TableGen/
H A DCTagsEmitter.cpp73 const auto &Defs = Records.getDefs(); in run() local
76 Tags.reserve(Classes.size() + Defs.size()); in run()
79 for (const auto &D : Defs) in run()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td57 // AL is really implied by AX, but the registers in Defs must match the
60 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
85 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
95 let Defs = [AX,DX,EFLAGS], Uses = [AX] in
100 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
105 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
112 let Defs = [AL,EFLAGS,AX], Uses = [AL] in
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H A DX86InstrTSX.td26 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
36 let Defs = [EFLAGS] in
H A DX86InstrExtension.td15 let Defs = [AX], Uses = [AL] in
18 let Defs = [EAX], Uses = [AX] in
22 let Defs = [AX,DX], Uses = [AX] in
25 let Defs = [EAX,EDX], Uses = [EAX] in
30 let Defs = [RAX], Uses = [EAX] in
34 let Defs = [RAX,RDX], Uses = [RAX] in
H A DX86InstrSystem.td17 let Defs = [RAX, RDX] in
21 let Defs = [RAX, RCX, RDX] in
79 let Defs = [AL], Uses = [DX] in
82 let Defs = [AX], Uses = [DX] in
85 let Defs = [EAX], Uses = [DX] in
89 let Defs = [AL] in
92 let Defs = [AX] in
95 let Defs = [EAX] in
443 let Defs = [RAX, RDX], Uses = [ECX] in
464 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
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H A DX86InstrInfo.td942 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
947 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
957 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1002 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1010 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1018 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1037 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1049 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1052 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
1056 let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
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H A DX86FloatingPoint.cpp845 unsigned Defs = Mask; in adjustLiveRegs() local
849 if (!(Defs & (1 << RegNo))) in adjustLiveRegs()
854 Defs &= ~(1 << RegNo); in adjustLiveRegs()
856 assert((Kills & Defs) == 0 && "Register needs killing and def'ing?"); in adjustLiveRegs()
859 while (Kills && Defs) { in adjustLiveRegs()
861 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs()
866 Defs &= ~(1 << DReg); in adjustLiveRegs()
891 while(Defs) { in adjustLiveRegs()
892 unsigned DReg = countTrailingZeros(Defs); in adjustLiveRegs()
896 Defs &= ~(1 << DReg); in adjustLiveRegs()
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/minix3/external/bsd/llvm/dist/clang/utils/TableGen/
H A DNeonEmitter.cpp491 void genBuiltinsDef(raw_ostream &OS, SmallVectorImpl<Intrinsic *> &Defs);
493 SmallVectorImpl<Intrinsic *> &Defs);
495 SmallVectorImpl<Intrinsic *> &Defs);
1957 SmallVectorImpl<Intrinsic *> &Defs) { in genBuiltinsDef() argument
1964 for (auto *Def : Defs) { in genBuiltinsDef()
1988 SmallVectorImpl<Intrinsic *> &Defs) { in genOverloadTypeCheckCode() argument
2002 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2084 SmallVectorImpl<Intrinsic *> &Defs) { in genIntrinsicRangeCheckCode() argument
2089 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2170 SmallVector<Intrinsic *, 128> Defs; in runHeader() local
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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DLiveVariables.h160 SmallVectorImpl<unsigned> &Defs);
161 void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
179 void runOnInstr(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
/minix3/external/bsd/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfoV3.td25 Defs = VolatileV3.Regs, isPredicable = 1,
41 Defs = VolatileV3.Regs, isPredicated = 1,
80 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
96 let Defs = [USR_OVF], Itinerary = ALU64_tc_2_SLOT23,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.td83 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
195 let Defs = [CC] in {
236 let isCall = 1, Defs = [R14D, CC] in {
273 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
327 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
390 let mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L] in
416 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
447 let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in
594 let Defs = [CC] in {
607 let Defs = [CC] in {
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H A DSystemZInstrFP.td44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
188 let Defs = [CC] in {
209 let Defs = [CC] in {
234 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
241 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
248 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
315 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
326 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
396 let Defs = [CC], CCValues = 0xF in {
/minix3/external/bsd/llvm/dist/llvm/test/TableGen/
H A Dforeach.td9 // CHECK: Defs

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