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Searched refs:CondCode (Results 1 – 25 of 58) sorted by relevance

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/minix3/external/bsd/llvm/dist/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h772 enum CondCode { enum
805 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
811 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
818 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
826 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
832 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
836 CondCode getSetCCSwappedOperands(CondCode Operation);
842 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
848 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
H A DAnalysis.h84 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
88 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
93 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
H A DSelectionDAG.h556 SDValue getCondCode(ISD::CondCode Cond);
719 ISD::CondCode Cond) {
745 SDValue True, SDValue False, ISD::CondCode Cond) {
1144 SDValue N2, ISD::CondCode Cond, SDLoc dl);
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp93 typedef std::tuple<int, int, AArch64CC::CondCode> CmpInfo;
99 CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
101 bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
204 static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) { in getAdjustedCmp()
218 MachineInstr *CmpMI, AArch64CC::CondCode Cmp) { in adjustCmp()
249 AArch64CC::CondCode Cmp; in modifyCmp()
280 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
284 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
294 AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm) in adjustTo()
347 AArch64CC::CondCode HeadCmp; in runOnMachineFunction()
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H A DAArch64ConditionalCompares.cpp165 AArch64CC::CondCode HeadCmpBBCC;
171 AArch64CC::CondCode CmpBBTailCC;
272 static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) { in parseCond()
276 CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in parseCond()
H A DAArch64ISelLowering.cpp900 unsigned CondCode = MI->getOperand(3).getImm(); in EmitF128CSEL() local
913 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB); in EmitF128CSEL()
965 static AArch64CC::CondCode changeIntCCToAArch64CC(ISD::CondCode CC) { in changeIntCCToAArch64CC()
993 static void changeFPCCToAArch64CC(ISD::CondCode CC, in changeFPCCToAArch64CC()
994 AArch64CC::CondCode &CondCode, in changeFPCCToAArch64CC() argument
995 AArch64CC::CondCode &CondCode2) { in changeFPCCToAArch64CC()
1002 CondCode = AArch64CC::EQ; in changeFPCCToAArch64CC()
1006 CondCode = AArch64CC::GT; in changeFPCCToAArch64CC()
1010 CondCode = AArch64CC::GE; in changeFPCCToAArch64CC()
1013 CondCode = AArch64CC::MI; in changeFPCCToAArch64CC()
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H A DAArch64BranchRelaxation.cpp347 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(0).getImm(); in invertBccCondition()
H A DAArch64InstrInfo.cpp189 AArch64CC::CondCode CC = (AArch64CC::CondCode)(int)Cond[0].getImm(); in ReverseBranchCondition()
420 AArch64CC::CondCode CC; in insertSelect()
425 CC = AArch64CC::CondCode(Cond[0].getImm()); in insertSelect()
929 AArch64CC::CondCode CC; in optimizeCompareInstr()
934 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 2).getImm(); in optimizeCompareInstr()
946 CC = (AArch64CC::CondCode)Instr.getOperand(IO - 1).getImm(); in optimizeCompareInstr()
2944 AArch64CC::CondCode CC = in optimizeCondBranch()
2945 (AArch64CC::CondCode)DefMI->getOperand(3).getImm(); in optimizeCondBranch()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.cpp38 enum CondCode { enum
137 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
150 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
161 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
221 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
243 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
297 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
306 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
420 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrInfo.h32 enum CondCode { enum
63 unsigned GetCondBranchFromCond(CondCode CC);
67 unsigned getSETFromCond(CondCode CC, bool HasMemoryOperand = false);
71 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
75 CondCode getCondFromCMovOpc(unsigned Opc);
79 CondCode GetOppositeBranchCondition(CondCode CC);
H A DX86InstrInfo.cpp2708 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { in getCondFromBranchOpc()
2731 static X86::CondCode getCondFromSETOpc(unsigned Opc) { in getCondFromSETOpc()
2754 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) { in getCondFromCMovOpc()
2808 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { in GetCondBranchFromCond()
2832 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { in GetOppositeBranchCondition()
2857 static X86::CondCode getSwappedCondition(X86::CondCode CC) { in getSwappedCondition()
2875 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) { in getSETFromCond()
2901 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, in getCMovFromCond()
3014 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); in AnalyzeBranch()
3076 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); in AnalyzeBranch()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
H A DMipsInstPrinter.cpp37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
261 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
/minix3/external/bsd/llvm/dist/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td523 class CondCode; // ISD::CondCode enums
524 def SETOEQ : CondCode; def SETOGT : CondCode;
525 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
526 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
527 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
528 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
530 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
531 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
H A DTargetLowering.h639 getCondCodeAction(ISD::CondCode CC, MVT VT) const { in getCondCodeAction()
652 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const { in isCondCodeLegal()
1295 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1587 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1593 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
1940 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2080 ISD::CondCode &CCCode, SDLoc DL) const;
2193 ISD::CondCode Cond, bool foldBooleans,
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h192 enum CondCode { // Meaning (integer) Meaning (floating-point) enum
213 inline static const char *getCondCodeName(CondCode Code) { in getCondCodeName()
235 inline static CondCode getInvertedCondCode(CondCode Code) { in getInvertedCondCode()
238 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1); in getInvertedCondCode()
245 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) { in getNZCVToSatisfyCondCode()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/
H A DAnalysis.cpp161 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
183 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
198 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp256 const ISD::CondCode Cond; in ARMTargetLowering()
1214 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1231 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1237 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1239 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1241 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1242 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1243 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
1244 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1245 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp58 AArch64CC::CondCode parseCondCodeString(StringRef Cond);
199 AArch64CC::CondCode Code;
243 struct CondCodeOp CondCode; member
275 CondCode = o.CondCode; in AArch64Operand()
337 AArch64CC::CondCode getCondCode() const { in getCondCode()
339 return CondCode.Code; in getCondCode()
1622 CreateCondCode(AArch64CC::CondCode Code, SMLoc S, SMLoc E, MCContext &Ctx) { in CreateCondCode()
1624 Op->CondCode.Code = Code; in CreateCondCode()
2213 AArch64CC::CondCode AArch64AsmParser::parseCondCodeString(StringRef Cond) { in parseCondCodeString()
2214 AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower()) in parseCondCodeString()
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/minix3/external/bsd/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h174 unsigned CondCode = 0) const;
/minix3/external/bsd/llvm/dist/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1042 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); in printCondCode()
1048 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); in printInverseCondCode()
/minix3/external/bsd/llvm/dist/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp1149 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1150 ISD::CondCode InverseCC = in LowerSELECT_CC()
1157 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InverseCC); in LowerSELECT_CC()
1184 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1186 ISD::CondCode CCSwapped = ISD::getSetCCSwappedOperands(CCOpcode); in LowerSELECT_CC()
1192 ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT.isInteger()); in LowerSELECT_CC()
1204 ISD::CondCode CCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerSELECT_CC()
1973 ISD::CondCode NCC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in PerformDAGCombine()
1985 ISD::CondCode LHSCC = cast<CondCodeSDNode>(LHS.getOperand(4))->get(); in PerformDAGCombine()
/minix3/external/bsd/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp748 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in SoftenFloatOp_BR_CC()
787 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in SoftenFloatOp_SELECT_CC()
810 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SoftenFloatOp_SETCC()
1403 ISD::CondCode &CCCode, in FloatExpandSetCCOperands()
1433 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in ExpandFloatOp_BR_CC()
1526 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in ExpandFloatOp_SELECT_CC()
1544 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ExpandFloatOp_SETCC()
H A DSelectionDAGBuilder.h215 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
225 ISD::CondCode CC;
H A DLegalizeTypes.h292 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
366 ISD::CondCode &CCCode, SDLoc dl);
500 ISD::CondCode &CCCode, SDLoc dl);

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