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/llvm-project/clang/test/Sema/
H A Dext_vector_components.c11 float2 vec2, vec2_2; in test() local
17 vec2.z; // expected-error {{vector component access exceeds type 'float2'}} in test()
18 vec2.xyzw; // expected-error {{vector component access exceeds type 'float2'}} in test()
22 vec2 = vec4.s01; // legal, shorten in test()
23 vec2 = vec4.S01; // legal, shorten in test()
26 f = vec2.x; // legal, shorten in test()
32 vec2.x = f; in test()
33 …vec2.xx = vec2_2.xy; // expected-error {{vector is not assignable (contains duplicate components)}} in test()
34 vec2.yx = vec2_2.xy; in test()
43 vec2.a; // expected-error {{vector component access exceeds type 'float2'}} in test()
[all …]
/llvm-project/libcxx/benchmarks/algorithms/
H A Dequal.bench.cpp
H A Dmismatch.bench.cpp
/llvm-project/llvm/test/CodeGen/X86/avx512-shuffles/
H A Dshuffle-interleave.ll4 define <4 x float> @test_4xfloat_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2) {
9 %res = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
12 define <4 x float> @test_4xfloat_masked_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x floa…
20 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
26 define <4 x float> @test_4xfloat_zero_masked_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x…
33 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
38 define <4 x float> @test_4xfloat_masked_shuff_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x floa…
46 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 1, i32 2, i32 7, i32 6>
52 define <4 x float> @test_4xfloat_zero_masked_shuff_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x…
59 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 1, i32 2, i32 7, i32 6>
[all …]
H A Dshuffle-vec.ll6 define <8 x float> @test_8xfloat_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2) {
11 …%res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, …
14 define <8 x float> @test_8xfloat_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x floa…
22 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
28 define <8 x float> @test_8xfloat_zero_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x…
35 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
40 define <8 x float> @test_8xfloat_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x floa…
48 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
54 define <8 x float> @test_8xfloat_zero_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x…
61 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
[all …]
H A Dunpack.ll4 define <4 x float> @test_4xfloat_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2) {
9 %res = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
12 define <4 x float> @test_4xfloat_masked_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x…
20 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
26 define <4 x float> @test_4xfloat_zero_masked_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2,…
33 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
38 define <4 x float> @test_4xfloat_masked_unpack_low_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x…
46 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
52 define <4 x float> @test_4xfloat_zero_masked_unpack_low_mask1(<4 x float> %vec1, <4 x float> %vec2,…
59 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
[all …]
H A Din_lane_permute.ll14 define <4 x float> @test_masked_4xfloat_perm_mask0(<4 x float> %vec, <4 x float> %vec2, <4 x float>…
24 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
40 define <4 x float> @test_masked_4xfloat_perm_mask1(<4 x float> %vec, <4 x float> %vec2, <4 x float>…
50 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
66 define <4 x float> @test_masked_4xfloat_perm_mask2(<4 x float> %vec, <4 x float> %vec2, <4 x float>…
76 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
100 define <4 x float> @test_masked_4xfloat_perm_mask3(<4 x float> %vec, <4 x float> %vec2, <4 x float>…
110 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
135 define <4 x float> @test_masked_4xfloat_perm_mem_mask0(ptr %vp, <4 x float> %vec2, <4 x float> %mas…
145 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
[all …]
H A Dduplicate-low.ll12 define <2 x double> @test_masked_2xdouble_dup_low_mask0(<2 x double> %vec, <2 x double> %vec2, <2 x…
22 %res = select <2 x i1> %cmp, <2 x double> %shuf, <2 x double> %vec2
38 define <2 x double> @test_masked_2xdouble_dup_low_mask1(<2 x double> %vec, <2 x double> %vec2, <2 x…
48 %res = select <2 x i1> %cmp, <2 x double> %shuf, <2 x double> %vec2
73 define <2 x double> @test_masked_2xdouble_dup_low_mem_mask0(ptr %vp, <2 x double> %vec2, <2 x doubl…
83 %res = select <2 x i1> %cmp, <2 x double> %shuf, <2 x double> %vec2
100 define <2 x double> @test_masked_2xdouble_dup_low_mem_mask1(ptr %vp, <2 x double> %vec2, <2 x doubl…
110 %res = select <2 x i1> %cmp, <2 x double> %shuf, <2 x double> %vec2
135 define <4 x double> @test_masked_4xdouble_dup_low_mask0(<4 x double> %vec, <4 x double> %vec2, <4 x…
145 %res = select <4 x i1> %cmp, <4 x double> %shuf, <4 x double> %vec2
[all …]
H A Dduplicate-high.ll12 define <4 x float> @test_masked_4xfloat_dup_high_mask0(<4 x float> %vec, <4 x float> %vec2, <4 x fl…
22 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
38 define <4 x float> @test_masked_4xfloat_dup_high_mask1(<4 x float> %vec, <4 x float> %vec2, <4 x fl…
48 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
64 define <4 x float> @test_masked_4xfloat_dup_high_mask2(<4 x float> %vec, <4 x float> %vec2, <4 x fl…
74 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
90 define <4 x float> @test_masked_4xfloat_dup_high_mask3(<4 x float> %vec, <4 x float> %vec2, <4 x fl…
100 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
116 define <4 x float> @test_masked_4xfloat_dup_high_mask4(<4 x float> %vec, <4 x float> %vec2, <4 x fl…
126 %res = select <4 x i1> %cmp, <4 x float> %shuf, <4 x float> %vec2
[all …]
H A Dshuffle.ll12 define <16 x i8> @test_masked_16xi8_perm_mask0(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
21 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
36 define <16 x i8> @test_masked_16xi8_perm_mask1(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
45 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
60 define <16 x i8> @test_masked_16xi8_perm_mask2(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
69 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
92 define <16 x i8> @test_masked_16xi8_perm_mask3(<16 x i8> %vec, <16 x i8> %vec2, <16 x i8> %mask) {
101 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
126 define <16 x i8> @test_masked_16xi8_perm_mem_mask0(ptr %vp, <16 x i8> %vec2, <16 x i8> %mask) {
136 %res = select <16 x i1> %cmp, <16 x i8> %shuf, <16 x i8> %vec2
[all …]
H A Dpermute.ll13 define <16 x i16> @test_masked_16xi16_perm_mask0(<16 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) {
23 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
39 define <16 x i16> @test_masked_16xi16_perm_mask1(<16 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) {
49 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
65 define <16 x i16> @test_masked_16xi16_perm_mask2(<16 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) {
75 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
100 define <16 x i16> @test_masked_16xi16_perm_mask3(<16 x i16> %vec, <16 x i16> %vec2, <16 x i16> %mask) {
110 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
136 define <16 x i16> @test_masked_16xi16_perm_mem_mask0(ptr %vp, <16 x i16> %vec2, <16 x i16> %mask) {
146 %res = select <16 x i1> %cmp, <16 x i16> %shuf, <16 x i16> %vec2
[all...]
H A Dpartial_permute.ll18 define <8 x i16> @test_masked_16xi16_to_8xi16_perm_mask0(<16 x i16> %vec, <8 x i16> %vec2, <8 x i16> %mask) {
30 %res = select <8 x i1> %cmp, <8 x i16> %shuf, <8 x i16> %vec2
48 define <8 x i16> @test_masked_16xi16_to_8xi16_perm_mask1(<16 x i16> %vec, <8 x i16> %vec2, <8 x i16> %mask) {
60 %res = select <8 x i1> %cmp, <8 x i16> %shuf, <8 x i16> %vec2
78 define <8 x i16> @test_masked_16xi16_to_8xi16_perm_mask2(<16 x i16> %vec, <8 x i16> %vec2, <8 x i16> %mask) {
90 %res = select <8 x i1> %cmp, <8 x i16> %shuf, <8 x i16> %vec2
119 define <8 x i16> @test_masked_16xi16_to_8xi16_perm_mask3(<16 x i16> %vec, <8 x i16> %vec2, <8 x i16> %mask) {
131 %res = select <8 x i1> %cmp, <8 x i16> %shuf, <8 x i16> %vec2
161 define <8 x i16> @test_masked_16xi16_to_8xi16_perm_mem_mask0(ptr %vp, <8 x i16> %vec2, <8 x i16> %mask) {
174 %res = select <8 x i1> %cmp, <8 x i16> %shuf, <8 x i16> %vec2
[all...]
/llvm-project/polly/lib/External/isl/
H A Disl_vec.c169 __isl_take isl_vec *vec2) in isl_vec_concat() argument
171 if (!vec1 || !vec2) in isl_vec_concat()
174 if (vec2->size == 0) { in isl_vec_concat()
175 isl_vec_free(vec2); in isl_vec_concat()
181 return vec2; in isl_vec_concat()
184 vec1 = isl_vec_extend(vec1, vec1->size + vec2->size); in isl_vec_concat()
188 isl_seq_cpy(vec1->el + vec1->size - vec2->size, vec2->el, vec2->size); in isl_vec_concat()
190 isl_vec_free(vec2); in isl_vec_concat()
194 isl_vec_free(vec2); in isl_vec_concat()
209 struct isl_vec *vec2; in isl_vec_dup() local
[all …]
/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A Dshufflevector.ll10 define amdgpu_kernel void @shufflevector_i16(<2 x i16> %vec1, <2 x i16> %vec2) {
49 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf00_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> zeroinitializer
50 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf01_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 0, i32 1>
51 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf10_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 1, i32 0>
52 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf11_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 1, i32 1>
53 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shuf02_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 0, i32 2>
54 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %shuf20_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 2, i32 0>
55 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf22_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 2, i32 2>
56 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shuf03_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <2 x i32> <i32 0, i32 3>
57 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shuf30_2 = shufflevector <2 x i16> %vec1, <2 x i16> %vec2, <
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dpacked-op-sel.ll254 %vec2 = insertelement <2 x half> %vec.ins0, half %neg.scalar1, i32 1
255 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2)
289 %vec2 = insertelement <2 x half> %vec.ins0, half %scalar1, i32 1
290 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2
292 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.vec2)
318 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4
320 %vec2.fneg = fsub <2 x half> <half -0.0, half -0.0>, %vec2
321 %vec2
[all...]
H A Dvni8-across-blocks.ll40 %vec2 = load <3 x i8>, ptr addrspace(1) %gep2
47 %tmp5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
76 %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
83 %tmp5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
116 %vec2 = load <5 x i8>, ptr addrspace(1) %gep2
123 %tmp5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
152 %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
159 %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
188 %vec2 = load <16 x i8>, ptr addrspace(1) %gep2
195 %tmp5 = phi <16 x i8> [ %vec1, %entry ], [ %vec2,
[all...]
/llvm-project/clang/test/CodeGen/
H A Dext-vector.c20 float2 vec2, vec2_2; variable
31 vec2 = vec4.xy; // shorten in test2()
32 f = vec2.x; // extract elt in test2()
35 vec2.x = f; // insert one. in test2()
36 vec2.yx = vec2; // reverse in test2()
315 vec2 = vec4.rg; in test_rgba()
324 vec2.r = f; in test_rgba()
326 vec2.gr = vec2; in test_rgba()
H A Darithmetic-fence-builtin.c41 __v2f32 vec1, vec2; in addit() local
42 vec1 = __arithmetic_fence(vec2); in addit()
44 vec2 = (vec2 + vec1); in addit()
/llvm-project/llvm/test/CodeGen/AArch64/
H A DlowerMUL-newload.ll4 define <4 x i16> @mlai16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
14 %v2 = sext <4 x i16> %vec2 to <4 x i32>
21 define <4 x i32> @mlai16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
32 %v2 = sext <4 x i16> %vec2 to <4 x i32>
58 %vec2 = load <4 x i16>, ptr %scevgep2, align 8
59 %v2 = sext <4 x i16> %vec2 to <4 x i32>
68 define <4 x i16> @addmuli16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
78 %v2 = sext <4 x i16> %vec2 to <4 x i32>
85 define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
96 %v2 = sext <4 x i16> %vec2 to <4 x i32>
[all …]
/llvm-project/libcxx/test/std/containers/sequences/deque/deque.modifiers/
H A Dpush_front_exception_safety.pass.cpp74 std::deque<CMyClass> vec2(vec); in main() local
83 assert(vec == vec2); in main()
91 C vec2(vec, test_allocator<CMyClass>(&alloc_stats)); in main() local
99 assert(vec==vec2); in main()
H A Dpush_back_exception_safety.pass.cpp75 std::deque<CMyClass> vec2(vec); in main() local
84 assert(vec == vec2); in main()
92 C vec2(vec, test_allocator<CMyClass>(&alloc_stats)); in main() local
100 assert(vec==vec2); in main()
/llvm-project/clang/test/PCH/
H A Dexprs.h79 extern double2 vec2, vec2b;
80 typedef typeof(vec2.x) ext_vector_element;
103 typedef typeof(__builtin_shufflevector(vec2, vec2b, 2, 1)) shuffle_expr;
107 typedef typeof(__builtin_convertvector(vec2, float2)) convert_expr;
/llvm-project/llvm/test/CodeGen/SPIRV/transcoding/
H A DOpVectorInsertDynamic_i16.ll19 ; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
20 ; CHECK: %[[#res]] = OpVectorInsertDynamic %[[#int16_2]] %[[#vec2]] %[[#v]] %[[#index]]
25 %vec2 = insertelement <2 x i16> %vec1, i16 8, i32 1
26 %res = insertelement <2 x i16> %vec2, i16 %v, i32 %index
/llvm-project/clang/test/CodeGenHLSL/builtins/
H A DScalarSwizzles.hlsl7 // CHECK: [[vec2:%.*]] = shufflevector <1 x i32> [[splat]], <1 x i32> poison, <2 x i32> zeroinitializer
8 // CHECK: ret <2 x i32> [[vec2]]
25 // CHECK: [[vec2:%.*]] = shufflevector <1 x i32> [[vec1]], <1 x i32> poison, <2 x i32> zeroinitializer
26 // CHECK: ret <2 x i32> [[vec2]]
55 // CHECK: [[vec2:%.*]] = shufflevector <1 x double> [[vec1]], <1 x double> poison, <2 x i32> zeroinitializer
56 // CHECK: ret <2 x double> [[vec2]]
104 // CHECK: [[vec2:%.*]] = shufflevector <1 x float> [[splat]], <1 x float> poison, <2 x i32> zeroinitializer
105 // CHECK: store <2 x float> [[vec2]], ptr [[vec2Ptr]], align 8
106 // CHECK: [[vec2:%.*]] = load <2 x float>, ptr [[vec2Ptr]], align 8
107 // CHECK: [[vec2Res:%.*]] = shufflevector <2 x float> [[vec2]], <
[all...]
/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
H A DInsertElement-inseltpoison.ll20 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
21 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2
31 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
32 %vec3 = insertelement <4 x i64> %vec2, i64 -3, i32 2

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