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/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
H A Dshufflevector.ll10 define amdgpu_kernel void @shufflevector_i16(<2 x i16> %vec1, <2 x i16> %vec2) {
12 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf00 = shufflevector <2 x i16> %vec1, <2 x i16> %vec1, <2 x i32> zeroinitializer
13 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf01 = shufflevector <2 x i16> %vec1, <2 x i16> %vec1, <2 x i32> <i32 0, i32 1>
14 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf10 = shufflevector <2 x i16> %vec1, <2 x i16> %vec1, <2 x i32> <i32 1, i32 0>
15 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %shuf11 = shufflevector <2 x i16> %vec1, <2 x i16> %vec1, <2 x i32> <i32 1, i32 1>
16 ; GFX9-10-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %shuf02 = shufflevector <2 x i16> %vec1, <
[all...]
/llvm-project/libcxx/benchmarks/algorithms/
H A Dfind.bench.cpp
H A Dfill.bench.cpp
H A Dequal.bench.cpp
H A Dmismatch.bench.cpp
H A Dcount.bench.cpp
H A Dfor_each.bench.cpp
/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-min-max.mir15 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
16 ; CHECK-NEXT: %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
20 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
21 %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
37 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
38 ; CHECK-NEXT: %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
42 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
43 %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
67 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF
68 %smin:_(<32 x s8>) = G_SMIN %vec, %vec1
[all …]
H A Dinsert-vector-elt-pr63826.ll16 %vec1 = insertelement <2 x i16> %vec, i16 1, i32 0
17 ret <2 x i16> %vec1
28 %vec1 = insertelement <2 x i8> %vec, i8 1, i32 0
29 ret <2 x i8> %vec1
40 %vec1 = insertelement <4 x i8> %vec, i8 1, i32 0
41 ret <4 x i8> %vec1
/llvm-project/llvm/test/Instrumentation/MemorySanitizer/
H A Dwith-call-type-size.ll7 %vec1 = insertelement <4 x i32> %vec, i32 %x, i1 %idx
8 ret <4 x i32> %vec1
16 %vec1 = insertelement <4 x i32> %vec, i32 %x, i2 %idx
17 ret <4 x i32> %vec1
25 %vec1 = insertelement <4 x i32> %vec, i32 %x, i8 %idx
26 ret <4 x i32> %vec1
34 %vec1 = insertelement <4 x i32> %vec, i32 %x, i9 %idx
35 ret <4 x i32> %vec1
43 %vec1 = insertelement <4 x i32> %vec, i32 %x, i16 %idx
44 ret <4 x i32> %vec1
[all …]
/llvm-project/llvm/test/CodeGen/X86/avx512-shuffles/
H A Dshuffle-interleave.ll4 define <4 x float> @test_4xfloat_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2) {
9 %res = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
12 define <4 x float> @test_4xfloat_masked_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x floa…
20 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
26 define <4 x float> @test_4xfloat_zero_masked_shuff_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x…
33 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 2, i32 1, i32 7, i32 5>
38 define <4 x float> @test_4xfloat_masked_shuff_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x floa…
46 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 1, i32 2, i32 7, i32 6>
52 define <4 x float> @test_4xfloat_zero_masked_shuff_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x…
59 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 1, i32 2, i32 7, i32 6>
[all …]
H A Dshuffle-vec.ll6 define <8 x float> @test_8xfloat_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2) {
11 …%res = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7, …
14 define <8 x float> @test_8xfloat_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x floa…
22 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
28 define <8 x float> @test_8xfloat_zero_masked_shuff_mask0(<8 x float> %vec1, <8 x float> %vec2, <8 x…
35 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
40 define <8 x float> @test_8xfloat_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x floa…
48 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
54 define <8 x float> @test_8xfloat_zero_masked_shuff_mask1(<8 x float> %vec1, <8 x float> %vec2, <8 x…
61 …%shuf = shufflevector <8 x float> %vec1, <8 x float> %vec2, <8 x i32> <i32 4, i32 5, i32 6, i32 7,…
[all …]
H A Dunpack.ll4 define <4 x float> @test_4xfloat_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2) {
9 %res = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
12 define <4 x float> @test_4xfloat_masked_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2, <4 x…
20 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
26 define <4 x float> @test_4xfloat_zero_masked_unpack_low_mask0(<4 x float> %vec1, <4 x float> %vec2,…
33 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
38 define <4 x float> @test_4xfloat_masked_unpack_low_mask1(<4 x float> %vec1, <4 x float> %vec2, <4 x…
46 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
52 define <4 x float> @test_4xfloat_zero_masked_unpack_low_mask1(<4 x float> %vec1, <4 x float> %vec2,…
59 %shuf = shufflevector <4 x float> %vec1, <4 x float> %vec2, <4 x i32> <i32 0, i32 4, i32 1, i32 5>
[all …]
/llvm-project/polly/lib/External/isl/
H A Disl_vec.c168 __isl_give isl_vec *isl_vec_concat(__isl_take isl_vec *vec1, in isl_vec_concat() argument
171 if (!vec1 || !vec2) in isl_vec_concat()
176 return vec1; in isl_vec_concat()
179 if (vec1->size == 0) { in isl_vec_concat()
180 isl_vec_free(vec1); in isl_vec_concat()
184 vec1 = isl_vec_extend(vec1, vec1->size + vec2->size); in isl_vec_concat()
185 if (!vec1) in isl_vec_concat()
188 isl_seq_cpy(vec1->el + vec1->size - vec2->size, vec2->el, vec2->size); in isl_vec_concat()
191 return vec1; in isl_vec_concat()
193 isl_vec_free(vec1); in isl_vec_concat()
[all …]
/llvm-project/llvm/test/CodeGen/AArch64/
H A Dsve-vector-interleave.ll4 …ne <vscale x 4 x half> @interleave2_nxv4f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1) {
11 … x 4 x half> @llvm.vector.interleave2.nxv4f16(<vscale x 2 x half> %vec0, <vscale x 2 x half> %vec1)
15 …ne <vscale x 8 x half> @interleave2_nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1) {
22 … x 8 x half> @llvm.vector.interleave2.nxv8f16(<vscale x 4 x half> %vec0, <vscale x 4 x half> %vec1)
26 … <vscale x 16 x half> @interleave2_nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1) {
33 … 16 x half> @llvm.vector.interleave2.nxv16f16(<vscale x 8 x half> %vec0, <vscale x 8 x half> %vec1)
37 …<vscale x 4 x float> @interleave2_nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1) {
44 …4 x float> @llvm.vector.interleave2.nxv4f32(<vscale x 2 x float> %vec0, <vscale x 2 x float> %vec1)
48 …<vscale x 8 x float> @interleave2_nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1) {
55 …8 x float> @llvm.vector.interleave2.nxv8f32(<vscale x 4 x float> %vec0, <vscale x 4 x float> %vec1)
[all …]
H A Dfixed-vector-interleave.ll5 define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) {
10 %retval = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1)
14 define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) {
31 %retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1)
35 define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) {
42 %retval = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1)
46 define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) {
62 %retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1)
66 define <8 x float> @interleave2_v8f32(<4 x float> %vec0, <4 x float> %vec1) {
73 %retval = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1)
[all...]
H A Darm64-copy-tuple.ll17 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
19 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
22 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
33 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
35 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
38 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
49 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
51 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
54 tail call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %vec0, <8 x i8> %vec1, ptr %addr)
65 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
[all …]
H A DlowerMUL-newload.ll4 define <4 x i16> @mlai16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
13 %v1 = sext <4 x i16> %vec1 to <4 x i32>
21 define <4 x i32> @mlai16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
31 %v1 = sext <4 x i16> %vec1 to <4 x i32>
55 %vec1 = load <4 x i16>, ptr %scevgep1, align 8
56 %v1 = sext <4 x i16> %vec1 to <4 x i32>
68 define <4 x i16> @addmuli16_trunc(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
77 %v1 = sext <4 x i16> %vec1 to <4 x i32>
85 define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
95 %v1 = sext <4 x i16> %vec1 to <4 x i32>
[all …]
/llvm-project/clang/test/CodeGenHLSL/builtins/
H A DScalarSwizzles.hlsl24 // CHECK: [[vec1:%.*]] = load <1 x i32>, ptr [[vec1Ptr]], align 4
25 // CHECK: [[vec2:%.*]] = shufflevector <1 x i32> [[vec1]], <1 x i32> poison, <2 x i32> zeroinitializer
34 // CHECK: [[vec1:%.*]] = load <1 x i32>, ptr [[vec1Ptr]], align 4
35 // CHECK: [[vec3:%.*]] = shufflevector <1 x i32> [[vec1]], <1 x i32> poison, <3 x i32> zeroinitializer
44 // CHECK: [[vec1:%.*]] = load <1 x i64>, ptr [[vec1Ptr]], align 8
45 // CHECK: [[vec4:%.*]] = shufflevector <1 x i64> [[vec1]], <1 x i64> poison, <4 x i32> zeroinitializer
54 // CHECK: [[vec1:%.*]] = load <1 x double>, ptr [[vec1Ptr]], align 8
55 // CHECK: [[vec2:%.*]] = shufflevector <1 x double> [[vec1]], <1 x double> poison, <2 x i32> zeroinitializer
64 // CHECK: [[vec1:%.*]] = load <1 x double>, ptr [[vec1Ptr]], align 8
65 // CHECK: [[vec3:%.*]] = shufflevector <1 x double> [[vec1]], <
[all...]
/llvm-project/llvm/test/CodeGen/AMDGPU/
H A Dbitcast-vector-extract.ll18 %vec1.bc = bitcast <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 9> to <8 x float>
19 store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
34 %vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <8 x float>
35 store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
50 %vec1.bc = bitcast <4 x i64> <i64 7, i64 7, i64 7, i64 9> to <4 x double>
51 store volatile <4 x double> %vec1.bc, ptr addrspace(1) %out
66 %vec1.bc = bitcast <16 x i16> <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 9> to <8 x float>
67 store volatile <8 x float> %vec1.bc, ptr addrspace(1) %out
H A Dpacked-op-sel.ll23 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
29 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %scalar0.broadcast)
54 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
61 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.broadcast)
86 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
93 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.broadcast)
118 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
126 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.neg.scalar0.broadcast)
151 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4
157 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <
[all...]
H A Dvni8-across-blocks.ll38 %vec1 = load <3 x i8>, ptr addrspace(1) %gep1
47 %tmp5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
74 %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
83 %tmp5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
114 %vec1 = load <5 x i8>, ptr addrspace(1) %gep1
123 %tmp5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
150 %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
159 %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
186 %vec1 = load <16 x i8>, ptr addrspace(1) %gep1
195 %tmp5 = phi <16 x i8> [ %vec1,
[all...]
/llvm-project/llvm/test/CodeGen/SPIRV/transcoding/
H A DOpVectorInsertDynamic_i16.ll18 ; CHECK: %[[#vec1:]] = OpCompositeInsert %[[#int16_2]] %[[#const1]] %[[#undef]] 0
19 ; CHECK: %[[#vec2:]] = OpCompositeInsert %[[#int16_2]] %[[#const2]] %[[#vec1]] 1
24 %vec1 = insertelement <2 x i16> undef, i16 4, i32 0
25 %vec2 = insertelement <2 x i16> %vec1, i16 8, i32 1
/llvm-project/clang/test/CodeGen/
H A Darithmetic-fence-builtin.c41 __v2f32 vec1, vec2; in addit() local
42 vec1 = __arithmetic_fence(vec2); in addit()
44 vec2 = (vec2 + vec1); in addit()
/llvm-project/llvm/test/Transforms/InstSimplify/ConstProp/
H A DInsertElement-inseltpoison.ll19 %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
20 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1
30 %vec1 = insertelement <4 x i64> poison, i64 -1, i32 0
31 %vec2 = insertelement <4 x i64> %vec1, i64 -2, i32 1

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