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/llvm-project/llvm/docs/AMDGPU/
H A DAMDGPUAsmGFX7.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vdst<amdgpu_synid_gfx7_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, …
42 …ref:`vdst<amdgpu_synid_gfx7_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, …
43 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`o…
44 … :ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>` :ref:`o…
45 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` …
46 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>` …
47 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_6802ce>` …
48 …ref:`vaddr<amdgpu_synid_gfx7_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx7_vdata_fd235e>` …
[all …]
H A DAMDGPUAsmGFX10.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx10_vcc>`, :ref:`vsrc0<a…
42 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`…
43 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`…
44 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`…
45 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`…
46 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx10_vsrc_6802ce>`…
47 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>` …
48 …ref:`vdst<amdgpu_synid_gfx10_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx10_vsrc_6802ce>`:…
[all …]
H A DAMDGPUAsmGFX9.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` …
42 …ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, …
43 …ref:`vdst<amdgpu_synid_gfx9_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, …
44 …ref:`vdst<amdgpu_synid_gfx9_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, …
45 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o…
46 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o…
47 … :ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>` :ref:`o…
48 …ref:`vaddr<amdgpu_synid_gfx9_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx9_vdata_6802ce>` …
[all …]
H A DAMDGPUAsmGFX940.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` …
42 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` …
43 …ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,…
44 …ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,…
45 …ref:`vdst<amdgpu_synid_gfx940_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,…
46 …ref:`vdst<amdgpu_synid_gfx940_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`,…
47 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_be4895>` …
48 …ref:`vaddr<amdgpu_synid_gfx940_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx940_vdata_9ad749>` …
[all …]
H A DAMDGPUAsmGFX90a.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` …
42 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_9ad749>` …
43 …ref:`vdst<amdgpu_synid_gfx90a_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,…
44 …ref:`vdst<amdgpu_synid_gfx90a_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,…
45 …ref:`vdst<amdgpu_synid_gfx90a_vdst_fa7dbd>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,…
46 …ref:`vdst<amdgpu_synid_gfx90a_vdst_0f48d1>`, :ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`,…
47 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_be4895>` …
48 …ref:`vaddr<amdgpu_synid_gfx90a_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx90a_vdata_9ad749>` …
[all …]
H A DAMDGPUAsmGFX1030.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vcc<amdgpu_synid_gfx1030_vcc>`, :ref:`vsr…
44 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802…
45 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802…
46 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802…
47 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802…
48 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx1030_vsrc_6802…
49 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802c…
50 …ref:`vdst<amdgpu_synid_gfx1030_vdst_89680f>`, :ref:`vsrc<amdgpu_synid_gfx1030_vsrc_6802c…
[all …]
H A DAMDGPUAsmGFX8.rst23 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
28 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
41 …ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` …
42 …ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, …
43 …ref:`vdst<amdgpu_synid_gfx8_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, …
44 …ref:`vdst<amdgpu_synid_gfx8_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, …
45 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o…
46 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o…
47 … :ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>` :ref:`o…
48 …ref:`vaddr<amdgpu_synid_gfx8_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx8_vdata_6802ce>` …
[all …]
H A DAMDGPUAsmGFX11.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` …
44 …ref:`vdst<amdgpu_synid_gfx11_vdst_bdb32f>`::ref:`b64<amdgpu_synid_gfx11_type_deviation_a14eb1>`, …
45 …ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee…
46 …ref:`vdst<amdgpu_synid_gfx11_vdst_89680f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee…
47 …ref:`vdst<amdgpu_synid_gfx11_vdst_bdb32f>`, :ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee…
48 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` …
49 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_fd235e>` …
50 …:ref:`vaddr<amdgpu_synid_gfx11_vaddr_f20ee4>`, :ref:`vdata<amdgpu_synid_gfx11_vdata_6802ce>` …
[all …]
H A DAMDGPUAsmGFX908.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, …
44 …ref:`vaddr<amdgpu_synid_gfx908_vaddr_0212e3>`, :ref:`vdata<amdgpu_synid_gfx908_vdata_6802ce>`, …
53 …ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, …
54 …ref:`vdata<amdgpu_synid_gfx908_vdata_fe1edf>`, :ref:`vaddr<amdgpu_synid_gfx908_vaddr_b73dc0>`, …
63 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`…
64 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref…
65 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`src0<amdgpu_synid_gfx908_src_73ab34>`::ref:`…
66 …ref:`vdst<amdgpu_synid_gfx908_vdst_89680f>`, :ref:`vsrc0<amdgpu_synid_gfx908_vsrc_6802ce>`::ref…
[all …]
H A DAMDGPUAsmGFX906.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …v_fmac_f32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
44 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx906_vsrc>`::ref:`m<amdgpu_sy…
45 …v_xnor_b32 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_…
46 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx906_vsrc>`, :ref:`vsrc1<a…
47 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_1>`::ref:`m<amdgpu_sy…
56 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_2>`::ref:`m<amdgpu_sy…
57 …_xnor_b32_e64 :ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_g…
66 …ref:`vdst<amdgpu_synid_gfx906_vdst>`, :ref:`src0<amdgpu_synid_gfx906_src_2>`::ref:`f16x2<amdgpu…
[all …]
H A DAMDGPUAsmGFX1011.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`f16x2<amdg…
44 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`i8x4<amdgp…
53 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`f16x2<amd…
54 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`vsrc0<amdgpu_synid_gfx1011_vsrc>`::ref:`i8x4<amdg…
63 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`f16x2<amdgp…
64 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`i8x4<amdgpu…
73 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src>`::ref:`f16x2<amdgp…
74 …ref:`vdst<amdgpu_synid_gfx1011_vdst>`, :ref:`src0<amdgpu_synid_gfx1011_src_2>`::ref:`i16x2<amd…
[all …]
H A DAMDGPUAsmGFX904.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_syni…
44 …ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_syni…
45 …ref:`vdst<amdgpu_synid_gfx904_vdst>`, :ref:`src0<amdgpu_synid_gfx904_src>`::ref:`m<amdgpu_syni…
H A DAMDGPUAsmGFX900.rst25 Notation used in this document is explained :ref:`here<amdgpu_syn_instruction_notation>`.
30 An overview of generic syntax and other features of AMDGPU instructions may be found :ref:`in this …
43 …ref:`vdst<amdgpu_synid_gfx900_vdst>`, :ref:`src0<amdgpu_synid_gfx900_src>`::ref:`m<amdgpu_syni…
44 …ref:`vdst<amdgpu_synid_gfx900_vdst>`, :ref:`src0<amdgpu_synid_gfx900_src>`::ref:`m<amdgpu_syni…
45 …ref:`vdst<amdgpu_synid_gfx900_vdst>`, :ref:`src0<amdgpu_synid_gfx900_src>`::ref:`m<amdgpu_syni…
/llvm-project/flang/test/HLFIR/order_assignments/
H A Dvector-subscripts-codegen.fir6 func.func @simple(%arg0: !fir.ref<!fir.array<100xf32>> , %arg1: !fir.ref<!fir.array<10xi64>> , %arg…
10 …niq_name = "_QFsimpleEx"} : (!fir.ref<!fir.array<100xf32>>, !fir.shape<1>) -> (!fir.ref<!fir.array…
12 …arg1(%2) {uniq_name = "y"} : (!fir.ref<!fir.array<10xi64>>, !fir.shape<1>) -> (!fir.ref<!fir.array…
13 …arg2(%2) {uniq_name = "z"} : (!fir.ref<!fir.array<10xf32>>, !fir.shape<1>) -> (!fir.ref<!fir.array…
15 hlfir.yield %4#0 : !fir.ref<!fir.array<10xf32>>
19 %5 = hlfir.designate %3#0 (%arg3) : (!fir.ref<!fir.array<10xi64>>, index) -> !fir.ref<i64>
20 %6 = fir.load %5 : !fir.ref<i64>
21 %7 = hlfir.designate %1#0 (%6) : (!fir.ref<!fir.array<100xf32>>, i64) -> !fir.ref<f32>
22 hlfir.yield %7 : !fir.ref<f32>
28 // CHECK-SAME: %[[VAL_0:.*]]: !fir.ref<!fir.array<100xf32>>,
[all …]
/llvm-project/flang/test/Analysis/AliasAnalysis/
H A Dalias-analysis-host-assoc.fir15 func.func @_QFtest1Pinner(%arg0: !fir.ref<!fir.array<10xi32>> {fir.bindc_name = "y"}, %arg1: !fir.r…
17 …%0 = fir.coordinate_of %arg1, %c0_i32 : (!fir.ref<tuple<!fir.box<!fir.array<10xi32>>>>, i32) -> !f…
18 %1 = fir.load %0 : !fir.ref<!fir.box<!fir.array<10xi32>>>
19 %2 = fir.box_addr %1 : (!fir.box<!fir.array<10xi32>>) -> !fir.ref<!fir.array<10xi32>>
23 … uniq_name = "_QFtest1Ex"} : (!fir.ref<!fir.array<10xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array…
26 …name = "_QFtest1FinnerEy"} : (!fir.ref<!fir.array<10xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array…
28 …designate %7#0 (%c1) {test.ptr = "test1_y(1)"} : (!fir.ref<!fir.array<10xi32>>, index) -> !fir.ref…
29 %9 = fir.load %8 : !fir.ref<i32>
31 …signate %5#0 (%c1_0) {test.ptr = "test1_x(1)"} : (!fir.ref<!fir.array<10xi32>>, index) -> !fir.ref…
32 hlfir.assign %9 to %10 : i32, !fir.ref<i32>
[all …]
/llvm-project/flang/test/HLFIR/
H A Dchar_extremum-bufferization.fir6 %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
7 …eparams %0#1 {uniq_name = "_QFmax1Ec1"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
8 %2:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
9 …eparams %2#1 {uniq_name = "_QFmax1Ec2"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
10 %4:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
11 …eparams %4#1 {uniq_name = "_QFmax1Ec3"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
19 // CHECK: %[[VAL_0:.*]]:2 = fir.unboxchar %[[ARG0]] : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,…
20 …%[[VAL_0]]#1 {uniq_name = "_QFmax1Ec1"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
21 // CHECK: %[[VAL_2:.*]]:2 = fir.unboxchar %[[ARG1]] : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,…
22 …%[[VAL_2]]#1 {uniq_name = "_QFmax1Ec2"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
[all …]
H A Dconcat-bufferization.fir7 %0:2 = fir.unboxchar %arg0 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
8 …%0#0 typeparams %0#1 {uniq_name = "c1"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
9 %2:2 = fir.unboxchar %arg1 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
10 …%2#0 typeparams %2#1 {uniq_name = "c2"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
11 %4:2 = fir.unboxchar %arg2 : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,?>>, index)
12 …%4#0 typeparams %4#1 {uniq_name = "c3"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
22 // CHECK: %[[VAL_3:.*]]:2 = fir.unboxchar %[[VAL_0]] : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,…
23 …eparams %[[VAL_3]]#1 {uniq_name = "c1"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
24 // CHECK: %[[VAL_5:.*]]:2 = fir.unboxchar %[[VAL_1]] : (!fir.boxchar<1>) -> (!fir.ref<!fir.char<1,…
25 …eparams %[[VAL_5]]#1 {uniq_name = "c2"} : (!fir.ref<!fir.char<1,?>>, index) -> (!fir.boxchar<1>, !…
[all …]
H A Dcount-elemental.fir3 …_QFPtest(%arg0: !fir.ref<!fir.array<4x7xi32>> {fir.bindc_name = "b"}, %arg1: !fir.ref<i32> {fir.bi…
8 …uniq_name = "_QFFtestEb"} : (!fir.ref<!fir.array<4x7xi32>>, !fir.shape<2>) -> (!fir.ref<!fir.array…
9 … hlfir.declare %arg1 {uniq_name = "_QFFtestErow"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3…
11 … = hlfir.declare %3 {uniq_name = "_QFFtestEtest"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3…
12 … hlfir.declare %arg2 {uniq_name = "_QFFtestEval"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i3…
13 %6 = fir.load %2#0 : !fir.ref<i32>
16 …%9 = hlfir.designate %1#0 (%7, %c1:%c7:%c1) shape %8 : (!fir.ref<!fir.array<4x7xi32>>, i64, index…
17 %10 = fir.load %5#0 : !fir.ref<i32>
20 %14 = hlfir.designate %9 (%arg3) : (!fir.box<!fir.array<7xi32>>, index) -> !fir.ref<i32>
21 %15 = fir.load %14 : !fir.ref<i32>
[all …]
H A Dassign-codegen.fir5 func.func @scalar_int(%arg0: !fir.ref<i32>, %arg1: !fir.ref<i32>) {
6 hlfir.assign %arg0 to %arg1 : !fir.ref<i32>, !fir.ref<i32>
10 // CHECK-SAME: %[[VAL_0:.*]]: !fir.ref<i32>,
11 // CHECK-SAME: %[[VAL_1:.*]]: !fir.ref<i32>) {
12 // CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref<i32>
13 // CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref<i32>
15 func.func @scalar_int_2(%arg0: !fir.ref<i32>) {
17 hlfir.assign %c42_i32 to %arg0 : i32, !fir.ref<i3
[all...]
H A Dopt-array-slice-assign.fir10 func.func @_QPtest1(%arg0: !fir.ref<!fir.array<8000x120x3xf32>> {fir.bindc_name = "x"}) {
19 %1:2 = hlfir.declare %0 {uniq_name = "_QFtest1Enew"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
21 %3:2 = hlfir.declare %2 {uniq_name = "_QFtest1Eold"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
23 %5:2 = hlfir.declare %arg0(%4) {uniq_name = "_QFtest1Ex"} : (!fir.ref<!fir.array<8000x120x3xf32>>, !fir.shape<3>) -> (!fir.ref<!fir.array<8000x120x3xf32>>, !fir.ref<!fi
[all...]
/llvm-project/flang/test/Transforms/
H A Dtbaa-with-dummy-scope.fir32 // CHECK: %[[VAL_5:.*]] = fir.load %{{.*}} : !fir.ref<f32>
33 // CHECK: fir.store %{{.*}} : !fir.ref<f32>
35 // CHECK: %[[VAL_9:.*]] = fir.load %{{.*}} {tbaa = [#[[$ATTR_12]]]} : !fir.ref<f32>
36 // CHECK: fir.store %{{.*}} {tbaa = [#[[$ATTR_13]]]} : !fir.ref<f32>
38 // CHECK: %[[VAL_13:.*]] = fir.load %{{.*}} {tbaa = [#[[$ATTR_14]]]} : !fir.ref<f32>
39 // CHECK: fir.store %{{.*}} {tbaa = [#[[$ATTR_15]]]} : !fir.ref<f32>
40 func.func @test1(%arg0: !fir.ref<f32> {fir.bindc_name = "x", fir.target}, %arg1: !fir.ref<f32> {fir…
42 … = #fir.var_attrs<target>, uniq_name = "_QFtestEx"} : (!fir.ref<f32>, !fir.dscope) -> !fir.ref<f32>
43 … = #fir.var_attrs<target>, uniq_name = "_QFtestEy"} : (!fir.ref<f32>, !fir.dscope) -> !fir.ref<f32>
44 %2 = fir.load %1 : !fir.ref<f32>
[all …]
H A Domp-map-info-finalization.fir8 fir.store %3 to %0 : !fir.ref<!fir.box<!fir.heap<i32>>>
9 %4:2 = hlfir.declare %0 {fortran_attrs = #fir.var_attrs<allocatable>, uniq_name = "test2"} : (!fir.ref<!fir.box<!fir.heap<i32>>>) -> (!fir.ref<!fir.box<!fir.heap<i32>>>, !fir.ref<!fir.box<!fir.heap<i32>>>)
12 fir.store %6 to %4#1 : !fir.ref<!fir.box<!fir.heap<i32>>>
18 %7 = fir.box_addr %2#1 : (!fir.box<!fir.array<?xi32>>) -> !fir.ref<!fir.array<?xi32>>
19 %8 = omp.map.info var_ptr(%4#1 : !fir.ref<!fir.box<!fir.heap<i32>>>, !fir.box<!fir.heap<i32>>) map_clauses(tofrom) capture(ByRef) -> !fir.ref<!fir.box<!fir.heap<i32>>>
20 %9 = omp.map.info var_ptr(%7 : !fir.ref<!fir.array<?xi32>>, !fir.array<?xi32>) map_clauses(from) capture(ByRef) bounds(%bounds) -> !fir.ref<!fi
[all...]
/llvm-project/clang/test/CodeGenCUDA/
H A Dlambda-reference-var.cu26 int &ref = global_device_var; in dev_capture_dev_ref_by_copy() local
27 [=](){ *out = ref;}(); in dev_capture_dev_ref_by_copy()
46 int &ref = global_device_var; in dev_capture_dev_ref_by_ref() local
47 [&](){ ref++; *out = ref;}(); in dev_capture_dev_ref_by_ref()
57 int &ref = global_device_var; in dev_ref() local
58 ref++; in dev_ref()
59 *out = ref; in dev_ref()
70 int &ref = global_device_var; in dev_lambda_ref() local
71 ref in dev_lambda_ref()
80 int &ref = global_host_var; host_capture_host_ref_by_copy() local
93 int &ref = global_host_var; host_capture_host_ref_by_ref() local
104 int &ref = global_host_var; host_ref() local
117 int &ref = global_host_var; host_lambda_ref() local
132 int &ref = global_host_var; dev_capture_host_ref_by_copy() local
[all...]
/llvm-project/flang/test/Lower/CUDA/
H A Dcuda-data-transfer.cuf45 ! CHECK: %[[ADEV:.*]]:2 = hlfir.declare %{{.*}}(%{{.*}}) {data_attr = #cuf.cuda<device>, uniq_name = "_QFsub1Eadev"} : (!fir.ref<!fir.array<10xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array<10xi32>>, !fir.ref<!fir.array<10xi32>>)
46 ! CHECK: %[[AHOST:.*]]:2 = hlfir.declare %{{.*}}(%{{.*}}) {uniq_name = "_QFsub1Eahost"} : (!fir.ref<!fir.array<10xi32>>, !fir.shape<1>) -> (!fir.ref<!fir.array<10xi32>>, !fir.ref<!fir.array<10xi32>>)
47 ! CHECK: %[[I:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = "_QFsub1Ei"} : (!fir.ref<i32>) -> (!fir.ref<i32>, !fir.ref<i32>)
48 ! CHECK: %[[M:.*]]:2 = hlfir.declare %{{.*}} {data_attr = #cuf.cuda<device>, uniq_name = "_QFsub1Em"} : (!fir.ref<i3
[all...]
/llvm-project/llvm/test/CodeGen/Thumb2/
H A Dconstant-islands.ll89 %ref.tmp = alloca %class.btVector3, align 4
90 %ref.tmp97 = alloca %class.btVector3, align 4
91 %ref.tmp98 = alloca float, align 4
92 %ref.tmp99 = alloca float, align 4
93 %ref.tmp100 = alloca float, align 4
94 %ref.tmp102 = alloca %class.btTransform, align 4
95 %ref.tmp107 = alloca %class.btVector3, align 4
96 %ref.tmp108 = alloca %class.btVector3, align 4
97 %ref.tmp109 = alloca float, align 4
98 %ref.tmp110 = alloca float, align 4
[all …]

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